ISP1583BSGA STEricsson, ISP1583BSGA Datasheet - Page 60

• Manufacturer Part Number: ISP1583BSGA
• Manufacturer: STEricsson

Specifications of ISP1583BSGA

• Operating Temperature (max): 85C
• Operating Temperature (min): -40C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Lead Free Status / RoHS Status: Compliant

Table 82.
ISP1583_11
Product data sheet
Bit
Symbol
Reset
Bus reset
Access
Bit
Symbol
Reset
Bus reset
Access
Bit
Symbol
Reset
Bus reset
Access
Bit
Symbol
Reset
Bus reset
Access
Interrupt register: bit allocation
EP6TX
EP2TX
VBUS
R/W
R/W
R/W
31
23
15
0
0
0
0
7
0
0
-
-
-
Each interrupt bit can individually be cleared by writing logic 1. The DMA Interrupt bit can
be cleared by writing logic 1 to the related interrupt source bit in the DMA Interrupt
Reason register, followed by writing logic 1 to the DMA bit of the Interrupt register.
Table 83.
Bit
31 to 26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
EP6RX
EP2RX
DMA
R/W
R/W
R/W
30
22
14
0
0
0
0
6
0
0
-
-
-
Interrupt register: bit description
Symbol
-
EP7TX
EP7RX
EP6TX
EP6RX
EP5TX
EP5RX
EP4TX
EP4RX
EP3TX
EP3RX
EP2TX
EP2RX
EP1TX
EP1RX
EP0TX
HS_STAT
EP5TX
EP1TX
R/W
R/W
R/W
29
21
13
0
0
0
0
5
0
0
-
-
-
Rev. 11 — 20 November 2009
reserved
Description
reserved
logic 1 indicates the endpoint 7 TX buffer as interrupt source
logic 1 indicates the endpoint 7 RX buffer as interrupt source
logic 1 indicates the endpoint 6 TX buffer as interrupt source
logic 1 indicates the endpoint 6 RX buffer as interrupt source
logic 1 indicates the endpoint 5 TX buffer as interrupt source
logic 1 indicates the endpoint 5 RX buffer as interrupt source
logic 1 indicates the endpoint 4 TX buffer as interrupt source
logic 1 indicates the endpoint 4 RX buffer as interrupt source
logic 1 indicates the endpoint 3 TX buffer as interrupt source
logic 1 indicates the endpoint 3 RX buffer as interrupt source
logic 1 indicates the endpoint 2 TX buffer as interrupt source
logic 1 indicates the endpoint 2 RX buffer as interrupt source
logic 1 indicates the endpoint 1 TX buffer as interrupt source
logic 1 indicates the endpoint 1 RX buffer as interrupt source
logic 1 indicates the endpoint 0 data TX buffer as interrupt source
RESUME
EP1RX
EP5RX
R/W
R/W
R/W
28
20
12
0
0
0
0
4
0
0
-
-
-
EP4TX
EP0TX
SUSP
R/W
R/W
R/W
27
19
11
0
0
0
0
3
0
0
-
-
-
Hi-Speed USB peripheral controller
EP4RX
EP0RX
PSOF
R/W
R/W
R/W
26
18
10
0
0
0
0
2
0
0
-
-
-
reserved
EP7TX
EP3TX
© ST-ERICSSON 2009. All rights reserved.
SOF
R/W
R/W
R/W
25
17
9
0
0
0
0
-
-
-
1
0
0
ISP1583
EP0SETUP
BRESET
EP7RX
EP3RX
R/W
R/W
R/W
R/W
24
16
8
0
0
0
0
0
0
0
0
1
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