AD6624AS Analog Devices Inc, AD6624AS Datasheet
AD6624AS
Specifications of AD6624AS
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AD6624AS Summary of contents
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FEATURES 80 MSPS Wide Band Inputs (14 Linear Bits Plus 3 RSSI) Dual High Speed Data Input Ports Four Independent Digital Receivers in Single Package Digital Resampling for Noninteger Decimation Rates Programmable Decimating FIR Filters Programmable Attenuator Control for ...
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AD6624 TABLE OF CONTENTS FEATURES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...
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... V Full IV V Full IV –3– AD6624 = unless otherwise noted.) A MIN MAX AD6624AS Typ Max Unit 2.5 2.675 V 3.3 3.6 V °C +25 +70 AD6624AS Typ Max Unit 3.3 V CMOS 5.0 V +0.8 V µ µ 3.3 V CMOS/TTL VDD – 0.2 V 0.2 0.4 V 400 250 ...
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... Full IV 16 Full IV 5.0 Full IV 5.0 Full IV 3.8 Full IV 3.7 Full IV 3.9 Full IV 1.9 Full IV 0.7 Full IV 2.4 Full IV 2.0 –4– AD6624AS Typ Max Unit ns 0.5 × CLK 0.5 × CLK 12 13.4 ns 14.0 ns 6.7 ns 6.9 ns 5.3 ns +4.7 ns +4 ...
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... All timing specifications valid over VDD range of 2.375 V to 2.675 V and VDDIO range all outputs unless otherwise specified. LOAD 3 Specification pertains to control signals: RW, (WR), DS, (RD), CS. Specifications subject to change without notice. REV Test AD6624AS Temp Level Min Typ Full IV 5.5 Full IV 1.0 ...
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AD6624 TIMING DIAGRAMS t CLK t CLKL CLK t CLKH t DLI LIA-A LIA-B LIB-A LIB-B Figure 1. Level Indicator Output Switching Characteristics RESET t SSF Figure 2. RESET Timing Requirements CLK IN[13:0] DATA EXP[2:0] Figure ...
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DSDO SCLK I I SDO 15 14 SDFE Figure 8. SDO, SDFE Switching Characteristics CLK t DDR DR Figure 9. CLK, DR Switching Characteristics SCLK t DSDR DR Figure 10. SCLK, DR Switching Characteristics REV DSDFE SCLK ...
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AD6624 TIMING DIAGRAMS—INM MICROPORT MODE CLK RD (DS HWR SC WR (RW HAM SAM A[2:0] VALID ADDRESS t t HAM SAM D[7:0] VALID DATA t DRDY RDY (DTACK) t ACC NOTES t 1. ...
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... JA Thermal measurements made in the horizontal position on a 4-layer board. Model Temperature Range AD6624AS –40°C to +70°C (Ambient) AD6624S/PCB CAUTION ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on the human body and test equipment and can discharge without detection. ...
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AD6624 VSS 1 PIN 1 INB5 2 IDENTIFIER INB4 3 INB3 4 INB2 5 INB1 6 VDD 7 INB0 8 IENB 9 LIB-B 10 LIB-A 11 VSS 12 CLK 13 EXPA0 14 EXPA1 15 EXPA2 16 VDD 17 INA13 18 ...
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Pin No. Mnemonic 1, 12, 38, 50, 65, 76, 102, 113 VSS 2–6 INB[5:1] 7, 17, 32, 44, 54, 81, 96, 118 VDD 8 INB0 9 IENB 10 LIB-B 11 LIB-A 13 CLK 14–16 EXPA[0:2] 18–21 INA[13:10] 22, 59, 71, ...
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AD6624 Pin No. Mnemonic 92 SCLK1 93 SDFS1 94 SDO1 95 SDIN1 97 SDFE1 98 DR1 99 SCLK2 100 SDFS2 101 SDO2 104 SDIN2 105 SDFE2 106 DR2 107 SCLK3 109 SDFS3 110 SDO3 111 SDIN3 112 SDFE3 114 DR3 ...
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ARCHITECTURE The AD6624 has four signal processing stages: a Frequency Translator, second order Resampling Cascaded Integrator Comb FIR filters (rCIC2), a fifth order Cascaded Integrator Comb FIR filter (CIC5), and a RAM Coefficient FIR filter (RCF). Multiple modes are supported ...
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AD6624 EXAMPLE FILTER RESPONSE 10 0 –10 –20 –30 –40 –50 –60 –70 –80 –90 –100 –110 0 –120 –130 –140 –150 –1000 –800 –600 –400 –200 0 200 kHz Figure 19. Filter Response The filter in Figure 19 is ...
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A typical application for this feature would be to take the data from an AD6600 Diversity ADC to one of the inputs of the AD6624. The A/B_OUT from that chip would be tied to the IEN. One channel within the ...
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AD6624 Input Data Scaling The AD6624 has two data input ports Input Port and a B Input Port. Each accepts 14-bit mantissa (twos complement integer) IN[13:0], a 3-bit exponent (unsigned integer) EXP[2:0] and the Input Enable (IEN). Both ...
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It also allows the AD6624 to be tailored in a system that employs the AD6600, but does not utilize all of its signal range. For example, if only the first four RSSI ranges are expected to occur, the ExpOff could ...
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AD6624 lowered, input data is replaced with zero values. During this period, the NCO continues to run such that when the IEN line is raised again, the NCO value will be at the value it would have otherwise been in ...
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S ceil log M rCIC 2 2 rCIC 2 × rCIC 2 OL input level CIC 2 × rCIC 2 rCIC 2 where input_level ...
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AD6624 Bit 11 of this register is used to invert the external exponent before internal calculation. This bit should be set HIGH for gain-ranging ADCs that use an increasing exponent to represent an increasing signal level. This bit should be ...
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I IN 160 20b I-RAM 256 20b C-RAM Q IN 160 20b Q-RAM Figure 27. RAM Coefficient Filter Block Diagram RCF Decimation Register Each RCF channel can be used to decimate the data rate. The decimation register is an 8-bit ...
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AD6624 Bit 8 is the RCF bank select bit used to program the register. When this bit is 0, the lowest block of 128 is selected (Taps 0 through 127). When high, the highest block is selected (Taps 128 through ...
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MICRO SHADOW REGISTER REGISTER I31 Q31 I31 Q31 FROM MICROPORT NCO FREQUENCY UPDATE HOLD-OFF COUNTER B0 B15 AD6624 CLK SOFT SYNC ENABLE TC ENB PIN SYNC ENABLE Figure 28. NCO Shadow Register and Hold-Off Counter Start ...
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AD6624 1. Note that the time from when RDY (Pin 57) goes high to when the NCO begins processing data is the contents of the NCO Freq Hold-Off counter (0x84) plus seven master clock cycles. 2. Write the NCO Freq ...
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SDFS (Serial Data Frame Sync) of another AD6624 chip or channel running in Serial Cascade mode. Serial Data Frame (Serial Cascade) Any of the AD6624 serial outputs may be operated ...
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AD6624 4 SDIV0 SCLK SDI AD6624 CH 0 SDO SDFS SDFE 10k 10k SBM0 Figure 35. Typical Serial Data Output Interface to DSP (Serial Slave Mode, SBM = 0) Serial Ports Cascaded Serial output ports may be cascaded on the ...
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Ch Address Register 00–7F Coefficient Memory (CMEM) 80 CHANNEL SLEEP 81 Soft_Sync Control Register 82 Pin_SYNC Control Register 83 Start Hold-Off Counter 84 NCO Frequency Hold-Off Counter 85 NCO Frequency Register 0 86 NCO Frequency Register 1 87 NCO Phase ...
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AD6624 Table VIII. Channel Address Memory Map (continued) Ch Address Register A5 BIST Signature for I Path A6 BIST Signature for Q Path BIST Outputs to Accumulate A8 RAM BIST Control Register A9 Serial Port Control Register ...
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Regardless of whether the chip is a Serial Bus Master Serial Slave mode, the AD6624 Serial Port functions are identi- cal except for the source of the SCLK and SDFS pins. SCLK SCLK is an output when ...
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AD6624 0x80: Channel Sleep Register This register contains the SLEEP bit for the channel. When this bit is high, the channel is placed in a low power state. When this bit is low, the channel processes data. Note that in ...
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When these bits are 11, the accumulator and sample CLK are determined by the rate at which the IEN pin toggles. The data that is captured on the rising edge of CLK after IEN transitions from high ...
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AD6624 Table IX. RCF Input Configurations Channel RCF Input Source when Bit Bit 8 is used as an extra address to allow a second block of 128 words of ...
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The SCLK can be generated and run maximum of 80 MHz. The serial division bits from this register are not used for serial port 0. The external SDIV [3:0] pins are used to determine this for Serial ...
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AD6624 Table XIII. Memory Map for Input Port Control Registers Ch Address Register 00 Lower Threshold A 01 Upper Threshold A 02 Dwell Time A 03 Gain Range A Control Register 04 Lower Threshold B 05 Upper Threshold B 06 ...
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Bit 4 causes the normal RSP data on serial channel replaced with read access data. This allows reading the internal registers over the serial bus. It should be noted that in the mode, any RSP data will ...
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AD6624 FRAME SCLK SDI Bit 3 determines if the input consists of a single channel or TDM channels such as when using the AD6600. If this bit is cleared, a single ADC is assumed. In this mode, LIA–A functions as ...
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EXTEST (3’b000) Places the IC into an external boundary-test mode and selects the boundary-scan register to be connected between TDI and TDO. During this, the boundary-scan regis- ter is accessed to drive test data off-chip via boundary outputs and receive ...
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AD6624 SEATING COPLANARITY 0.10 MAX OUTLINE DIMENSIONS 128-Lead Metric Quad Flat Package [MQFP] (S-128-1) Dimensions shown in millimeters 17.45 17.20 16.95 14.20 3.40 14.00 MAX 13.80 1.03 128 1 0.88 0.73 PLANE TOP VIEW (PINS DOWN 0.50 2.90 ...
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Revision History Location 3/04—Data Sheet changed from REV REV. B. Changes to ORDERING GUIDE . . . . . . . . . . . . . . . . . . . . . . . . ...
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