MCIMX27MJP4A Freescale, MCIMX27MJP4A Datasheet - Page 74

• Manufacturer Part Number: MCIMX27MJP4A
• Manufacturer: Freescale

Specifications of MCIMX27MJP4A

• Lead Free Status / RoHS Status: Compliant

Electrical Characteristics
74
1
Note:
Timing parameters are relevant only to SDR SDRAM. For the specific DDR SDRAM data related timing parameters, see
Table 41
SD10
SD6
SD7
SD8
SD9
ID
and
Address hold time
Address setup time
SDRAM access time
Data out hold time
Active to read/write command period
Table
SDR SDRAM CLK parameters are being measured from the 50%
point—that is, high is defined as 50% of signal value and low is defined as
50% of signal value. SD1 + SD2 does not exceed 7.5 ns for 133 MHz.
The timing parameters are similar to the ones used in SDRAM data
sheets—that is,
are driven by the ESDCTL at the negative edge of SDCLK and the
parameters are measured at maximum memory frequency.
Table 37. DDR/SDR SDRAM Read Cycle Timing Parameters (continued)
42.
1
Table 37
Parameter
i.MX27 and i.MX27L Data Sheet, Rev. 1.6
indicates SDRAM requirements. All output signals
NOTE
Symbol
tAH
tOH
tRC
tAS
tAC
Min
2.0
1.8
1.8
10
—
Freescale Semiconductor
Max
6.47
—
—
—
—
clock
Unit
ns
ns
ns
ns