MCIMX27MJP4A Freescale, MCIMX27MJP4A Datasheet - Page 67

• Manufacturer Part Number: MCIMX27MJP4A
• Manufacturer: Freescale

Specifications of MCIMX27MJP4A

• Lead Free Status / RoHS Status: Compliant

4.3.7
Figure
signals of the NFC at module level, and
(NFC) timing parameters are based on the internal NFC clock generated by the Clock Controller module,
where time T is the period of the NFC clock in ns. The relationship between the NFC clock and the external
timing parameters of the NFC is provided in
Table 35
22.17 MHz and 33.25 MHz. Assuming a 266 MHz FCLK (CPU clock), NFCDIV should be set to
divide-by-12 to generate a 22.17 MHz NFC clock and divide-by-8 to generate a 33.25 MHz NFC clock.
The user should compare the parameters of the selected NAND Flash memory with the NFC external
timing parameters to determine the proper NFC clock. The maximum NFC clock allowed is 66 MHz. It
should also be noted that the default NFC clock on power up is 16.63 MHz.
Freescale Semiconductor
MSHC_SCLK
MSHC_DATA
MSHC_BS
31,
Signal
also provides two examples of external timing parameters with NFC clock frequencies of
MSHC_DATA
MSHC_BS
Figure
Signal
NAND Flash Controller Interface (NFC)
32,
Cycle
H pulse length
L pulse length
Rise time
Fall time
Setup time
Hold time
Setup time
Hold time
Output delay time
Figure
Setup time
Hold time
Setup time
Hold time
Output delay time
Table 33. Serial Interface Timing Parameters (continued)
33, and
Parameter
Table 34. Parallel Interface Timing Parameters
Parameter
i.MX27 and i.MX27L Data Sheet, Rev. 1.6
Figure 34
Table 35
Table
show the relative timing requirements among different
lists the timing parameters. The NAND Flash Controller
35.
tSCLKwh
Symbol
tSCLKwl
Symbol
tSCLKc
tSCLKr
tBSsu
tSCLKf
tBSh
tBSsu
tDsu
tBSh
tDsu
tDh
tDd
tDh
tDd
Min.
—
5
5
5
5
Standards
Min
25
—
—
—
5
8
1
8
1
5
Standards
Max.
15
—
—
—
—
Max
10
10
15
—
—
—
—
—
—
—
Electrical Characteristics
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Unit
ns
ns
ns
ns
ns
Unit
67