HSP43216VC-52 Intersil, HSP43216VC-52 Datasheet - Page 12

• Manufacturer Part Number: HSP43216VC-52
• Manufacturer: Intersil

Specifications of HSP43216VC-52

• Lead Free Status / RoHS Status: Not Compliant

...X2,X1,X0
FIGURE 13. DOWN CONVERT AND DECIMATE FUNCTION
FIGURE 14. DOWN CONVERT AND DECIMATE FUNCTION
†
REAL OUTPUTS
R0 = X0(C0)-X2(C2)+X4(C4)-X6(C6)
R1 = -X2(C0)+X4(C2)-X6(C4)+X8(C6)
R2 = X4(C0)-X6(C2)+X8(C4)-X10(C6)
...,X4,X2,X0
...,X5,X3,X1
Indicates samples discarded by decimation process
†
†
†
†
REAL OUTPUTS
R0 = X0(C0)+0(C1)-X2(C2)+0(C3)+X4(C4)+0(C5)-X6(C6)
R1 = 0(C0)-X2(C1)+0(C2)+X4(C3)+0(C4)-X6(C5)+0(C6)
R2 = -X2(C0)+0(C1)+X4(C2)+0(C3)-X6(C4)+0(C5)+X4(C6)
R3 = 0(C0)+X4(C1)+0(C2)-X6(C3)+0(C4)+X4(C5)+0(C6)
I0 = 0(C0)-X1(C1)+0(C2)+X3(C3)+0(C4)-X5(C5)+0(C6)
I1 = -X1(C0)+0(C1)+X3(C2)+0(C3)-X5(C4)+0(C5)+X7(C6)
I2 = 0(C0)+X3(C1)+0(C2)-X5(C3)+0(C4)+X7(C5)+0(C6)
I3 = X3(C0)+0(C1)-X5(C2)+0(C3)+X7(C4)+0(C5)-X9(C6)
IMAGINARY OUTPUTS
1, 0,-1, 0...
COS(
SIN(-
0,-1,0,1...
USING TRANSVERSAL FILTERS
USING POLYPHASE FILTERS
1,-1,1,-1,..
-1,1,-1,1..
COS LO
SIN LO
n
n
π/2)
π/2)
C0 C1 C2 C3 C4 C5 C6
C0 C1 C2 C3 C4 C5 C6
HALFBAND FILTER
HALFBAND FILTER
EVEN TAP FILTER
12
ODD TAP FILTER
C0 C2 C4 C6
R
E
G
IMAGINARY OUTPUTS
I0 = -X1(C1)+X3(C3)-X5(C5)
I1 = X3(C1)-X5(C3)+X7(C5)
I2 = -X5(C1)+X7(C3)-X9(C5)
C1 C3 C5
2
2
...,R1,R0
...,I1,I0
...,I2,I0
...,R2,R0
HSP43216
The HSP43216’s implementation of Down Convert and
Decimate mode is analogous to the polyphase solution
shown in Figure 14. The part’s data flow diagram for this
mode is shown in Figure 15A and Figure 15B. As seen in
the figures, the input sample data is broken into even and
odd sample streams which feed the upper and lower
processing legs as described in the Decimate By 2 Mode
section. The data on each processing leg is then
modulated with the nonzero quadrature components of the
complex exponent (see Quadrature Down Convert
Section). Following this operation, the upper leg becomes
the processing chain for the real (In-phase) component of
the quadrature down conversion and the lower leg
processes the complex (Quadrature) component of the
down conversion. The filter processing block implements
the equivalent of a decimate by two Halfband filter on each
of the quadrature legs.
If internal multiplexing is specified (INT/EXT = 1), the upper
and lower processing legs are fed with even and odd
sample streams which are derived from data input through
AIN0-15. The input sample stream may be synchronized
with the zero degree phase term of the down converter LO
by using the SYNC control input. For example, an input
data sample will be fed into the real (upper) processing leg
and mixed with the zero degree cosine term of the
quadrature LO if it is input on the 4th CLK following the
assertion of SYNC as shown in Figure 16. The pipeline
delay through the real processing leg (upper leg) is 14
CLK’s and the delay through the imaginary processing leg
(lower leg) is 47 CLK’s. The complex samples output
through AOUT0-15 and BOUT0-15 are present for 2 CLK’s
since the quadrature streams have been decimated by two
in the filter processor.
October 6, 2008
FN3365.10