HSP43216VC-52 Intersil, HSP43216VC-52 Datasheet
HSP43216VC-52
Specifications of HSP43216VC-52
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HSP43216VC-52 Summary of contents
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... HSP43216JC-52Z HSP43216VC-52 HSP 43216VC-52 HSP43216VC-52Z (Note) HSP 43216VC-52Z NOTE: These Intersil Pb-free plastic packaged products employ special Pb-free material sets, molding compounds/die attach materials, and 100% matte tin plate plus anneal (e3 termination finish, which is RoHS compliant and compatible with both SnPb and Pb-free soldering operations). Intersil ...
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Block Diagram AIN0-15 INPUT DATA FLOW CONTROLLER BIN0-15 SYNC USB/LSB MODE0-1 INT/EXT RND0-2 FMT OEA OEB CLK Pinouts SYNC USB/LSB INT/EXT BIN0 BIN1 BIN2 BIN3 BIN4 BIN5 BIN6 BIN7 BIN8 BIN9 BIN10 BIN11 BIN12 ...
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Pinouts (Continued) SYNC USB/LSB INT/EXT BIN0 BIN1 BIN2 BIN3 BIN4 BIN5 BIN6 BIN7 BIN8 BIN9 BIN10 BIN11 BIN12 BIN13 BIN14 BIN15 RND0 RND1 Pin Description NAME TYPE VCC - +5V Power. GND - Ground. CLK I Clock Input. (CMOS LEVEL). ...
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QUADRATURE S DOWN CONVERT INPUT DATA FLOW PROCESSOR CONTROLLER † R AIN0- † BIN0- CLK MODE0-1 SYNC INT/EXT ...
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For added flexibility, a spectrally reversed version of the above process may be realized by configuring the Down Convert processor to impart a positive f the input signal. This has the effect of centering the lower sideband of the input ...
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TABLE 3. FREQUENCY RESPONSE OF THE 67-TAP HALFBAND FILTER NORMALIZED TO THE MODE SPECIFIC SAMPLE RATE FREQUENCY MAGNITUDE FREQUENCY (NORMALIZED) (dB) (NORMALIZED) 0.000000 -0.000256 0.125000 0.003906 -0.000143 0.128906 0.007812 -0.000071 0.132812 0.011719 -0.000013 0.136719 0.015625 -0.000004 0.140625 0.019531 -0.000001 0.144531 ...
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Quadrature Up Convert Processor S The f /4 Quadrature Up Convert Processor provides the spectral shift used to construct a real signal from a S complex sample stream. The operation performed is equivalent to multiplying ...
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TABLE 5. OUTPUT ROUNDING CONTROL RND 2-0 ROUND FUNCTION 000 Round output to 8-bits, AOUT15-8 and BOUT15-8, zero lower bits. 001 Round output to 9-bits, AOUT15-7 and BOUT15-7, zero lower bits. 010 Round output to 10-bits, AOUT15-6 and BOUT15-6, zero ...
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AIN0- † † Clocked at CLK/2 FIGURE 7A. DATA FLOW DIAGRAM FOR DECIMATE BY 2 FILTER MODE (INT/EXT = AIN0- ...
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TAP HALFBAND FILTER ..,X2,X1,X0 ..X1,0,X0 Y(0) = 0(C0)+X0(C1)+0(C2)+X1(C3)+0(C4)+X2(C5)+0(C6) Y(1) = X0(C0)+0(C1)+X1(C2)+0(C3)+X2(C4)+0(C5)+X3(C6) Y(2) = 0(C0)+X1(C1)+0(C2)+X2(C3)+0(C4)+X3(C5)+0(C6) Y(3) = X1(C0)+0(C1)+X2(C2)+0(C3)+X3(C4)+0(C5)+X4(C6) FIGURE 9. TRANSVERSAL IMPLEMENTATION OF INTERPOLATE BY TWO HALFBAND FILTER EVEN TAP FILTER ..,Y5,Y3,Y1 ...
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If internal multiplexing is selected (INT/EXT = 1), the data stream input through AIN0-15 is fed to both the upper and lower processing legs as shown in Figure 11A. The output of each processing leg is then multiplexed together to ...
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HALFBAND FILTER ...X2,X1, 0,-1, 0... π/2) n COS( HALFBAND FILTER 0,-1,0,1... π/2) n SIN(- REAL OUTPUTS R0 = X0(C0)+0(C1)-X2(C2)+0(C3)+X4(C4)+0(C5)-X6(C6) † 0(C0)-X2(C1)+0(C2)+X4(C3)+0(C4)-X6(C5)+0(C6 ...
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AIN0- † † Clocked at CLK/2 FIGURE 15A. DATA FLOW DIAGRAM FOR DOWN CONVERT AND DECIMATE MODE (INT/EXT = 1) AIN0- ...
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INPUT SIGNAL SPECTRUM - INTERPOLATED SIGNAL FILTER PASSBAND ’ ’ UPCONVERTED SIGNAL ’ ’ ...
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AIN0- † 1 BIN0- Clock at Input data rate, CLK/2 † FIGURE 21A. DATA FLOW DIAGRAM FOR QUADRATURE TO REAL ...
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Absolute Maximum Ratings Supply Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...
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AC Electrical Specifications (Note 7) PARAMETER CLK Period CLK High CLK Low Setup Time AIN0-15, BIN0-15 to CLK Hold Time AIN0-15, BIN0-15 from CLK MODE0-1, RND0-2, INT/EXT, SYNC, USB/LSB Setup Time to CLK MODE0-1, RND0-2, INT/EXT, SYNC, USB/LSB Hold Time ...
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Waveforms CLK AIN0-15, BIN-15 MODE0-1, RND0-2, INT/EXT, SYNC, USB/LSB AOUT0-15, BOUT0-15 OE 2.0V 0.8V 18 HSP43216 FIGURE 23. TIMING RELATIVE TO CLK t r ...
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Plastic Leaded Chip Carrier Packages (PLCC) 0.042 (1.07) 0.042 (1.07) 0.048 (1.22) 0.056 (1.42) PIN (1) IDENTIFIER 0.050 (1.27 0.020 (0.51) MAX 3 PLCS 0.026 (0.66) 0.032 (0.81) 0.045 (1.14) MIN VIEW “A” ...
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... Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use ...