CY7C0853V-100BBI Cypress Semiconductor Corp, CY7C0853V-100BBI Datasheet - Page 9

• Manufacturer Part Number: CY7C0853V-100BBI
• Manufacturer: Cypress Semiconductor Corp

Specifications of CY7C0853V-100BBI

• Density: 9Mb
• Access Time (max): 4.7ns
• Sync/async: Synchronous
• Architecture: SDR
• Clock Freq (max): 100MHz
• Operating Supply Voltage (typ): 3.3V
• Address Bus: 18b
• Package Type: FBGA
• Operating Temp Range: -40C to 85C
• Number Of Ports: 2
• Supply Current: 310mA
• Operating Supply Voltage (min): 3.135V
• Operating Supply Voltage (max): 3.465V
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 172
• Word Size: 36b
• Number Of Words: 256K
• Lead Free Status / RoHS Status: Not Compliant

Counter Interrupt
The counter interrupt (CNTINT) is asserted LOW when an
increment operation results in the unmasked portion of the
counter register being all “1s.” It is deasserted HIGH when an
Increment operation results in any other value. It is also
de-asserted by Counter Reset, Counter Load, Mask Reset and
Mask Load operations, and by MRST.
Retransmit
Retransmit is a feature that allows the Read of a block of memory
more than once without the need to reload the initial address.
This eliminates the need for external logic to store and route
data. It also reduces the complexity of the system design and
saves board space. An internal “mirror register” is used to store
the initially loaded address counter value. When the counter
unmasked portion reaches its maximum value set by the mask
register, it wraps back to the initial value stored in this “mirror
register.” If the counter is continuously configured in increment
mode, it increments again to its maximum value and wraps back
to the value initially stored into the “mirror register.” Thus, the
repeated access of the same data is allowed without the need
for any external logic.
Mask Reset Operation
The mask register is reset to all “1s,” which unmasks every bit of
the counter. Master reset (MRST) also resets the mask register
to all “1s.”
Document #: 38-06070 Rev. *H
Mask Load Operation
The mask register is loaded with the address value presented at
the address lines. Not all values permit correct increment opera-
tions. Permitted values are of the form 2
most significant bit to the least significant bit, permitted values
have zero or more “0s,” one or more “1s,” or one “0.” Thus
1FFFF, 003FE, and 00001 are permitted values, but 1F0FF,
003FC, and 00000 are not.
Mask Readback Operation
The internal value of the mask register can be read out on the
address lines. Readback is pipelined; the address is valid t
after the next rising edge of the port’s clock. If mask readback
occurs while the port is enabled (CE0 LOW and CE1 HIGH), the
data lines (DQs) is three-stated. Figure 4 on page 10 shows a
block diagram of the operation.
Counting by Two
When the least significant bit of the mask register is “0,” the
counter increments by two. This may be used to connect the
CY7C0850AV/CY7C0851AV/CY7C0852AV as a 72-bit single
port SRAM in which the counter of one port counts even
addresses and the counter of the other port counts odd
addresses. This even-odd address scheme stores one half of the
72-bit data in even memory locations, and the other half in odd
memory locations.
CY7C0850AV, CY7C0851AV
CY7C0852AV, CY7C0853AV
n
– 1 or 2
n
– 2. From the
Page 9 of 32
CM2
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