M48Z128V-85PM1 STMicroelectronics, M48Z128V-85PM1 Datasheet - Page 9

• Manufacturer Part Number: M48Z128V-85PM1
• Manufacturer: STMicroelectronics
• Type: NVSRAMr

Specifications of M48Z128V-85PM1

• Word Size: 8b
• Organization: 128Kx8
• Density: 1Mb
• Interface Type: Parallel
• Access Time (max): 85ns
• Operating Supply Voltage (typ): 3.3V
• Package Type: PMDIP
• Operating Temperature Classification: Commercial
• Operating Supply Voltage (max): 3.6V
• Operating Supply Voltage (min): 3V
• Operating Temp Range: 0C to 70C
• Pin Count: 32
• Mounting: Through Hole
• Supply Current: 50mA
• Lead Free Status / RoHS Status: Supplier Unconfirmed

M48Z128, M48Z128Y, M48Z128V
2.2
Note:
Note:
WRITE mode
The M48Z128/Y/V is in the WRITE mode whenever W and E are active. The start of a
WRITE is referenced from the latter occurring falling edge of W or E. A WRITE is terminated
by the earlier rising edge of W or E.
The addresses must be held valid throughout the cycle. E or W must return high for
minimum of t
cycle. Data-in must be valid t
t
although, if the output bus has been activated by a low on E and G, a low on W will disable
the outputs t
Figure 6.
Output enable (G) = high.
Figure 7.
Output enable (G) = high.
EHDX
A0-A16
E
W
DQ0-DQ7
A0-A16
E
W
DQ0-DQ7
afterward. G should be kept high during WRITE cycles to avoid bus contention;
WLQZ
EHAX
WRITE enable controlled, WRITE AC waveforms
Chip enable controlled, WRITE AC waveforms
after W falls.
from E or t
tAVEL
tAVEL
tAVWL
tAVWL
DVWH
WHAX
Doc ID 2426 Rev 5
tWLQZ
prior to the end of WRITE and remain valid for t
from W prior to the initiation of another READ or WRITE
tAVWH
tAVEH
tWLWH
VALID
VALID
tAVAV
tAVAV
tELEH
tDVEH
tDVWH
DATA INPUT
DATA INPUT
tWHDX
tEHDX
tWHQX
Operating modes
tEHAX
tWHAX
WHDX
AI01198
AI01199
9/20
or