m48z12 STMicroelectronics, m48z12 Datasheet

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m48z12

Manufacturer Part Number
m48z12
Description
5v, 16kbit 2kb X 8 Zeropower Sram
Manufacturer
STMicroelectronics
Datasheet

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Features
November 2007
Integrated, ultra low power SRAM and power-
fail control circuit
Unlimited WRITE cycles
READ cycle time equals WRITE cycle time
Automatic power-fail chip deselect and WRITE
protection
WRITE protect voltages
(V
– M48Z02: V
– M48Z12: V
Self-contained battery in the CAPHAT™ DIP
package
Pin and function compatible with JEDEC
standard 2K x 8 SRAMs
RoHS compliant
– Lead-free second level interconnect
PFD
4.5V ≤ V
4.2V ≤ V
= Power-fail deselect voltage):
PFD
PFD
CC
CC
≤ 4.5V
≤ 4.75V
= 4.75 to 5.5V;
= 4.5 to 5.5V;
5V, 16Kbit (2Kb x 8) ZEROPOWER
Rev 5
24
battery CAPHAT™
PCDIP24 (PC)
1
M48Z02
M48Z12
®
SRAM
www.st.com
1/20
1

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m48z12 Summary of contents

Page 1

... WRITE protect voltages (V = Power-fail deselect voltage): PFD – M48Z02 4.75 to 5.5V; CC 4.5V ≤ V ≤ 4.75V PFD – M48Z12 4.5 to 5.5V; CC 4.2V ≤ V ≤ 4.5V PFD ■ Self-contained battery in the CAPHAT™ DIP package ■ Pin and function compatible with JEDEC standard SRAMs ■ ...

Page 2

Contents 1 Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...

Page 3

List of tables Table 1. Signal names . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...

Page 4

List of figures Figure 1. Logic diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...

Page 5

... Table 1. Signal names A0-A10 DQ0-DQ7 ® RAM non-volatile static RAM which is pin and A0-A10 W M48Z02 M48Z12 Address inputs Data inputs / outputs Chip enable Output enable WRITE enable Supply voltage Ground DQ0-DQ7 AI01186 5/20 ...

Page 6

... LITHIUM CELL VOLTAGE SENSE SWITCHING 6/ M48Z02 19 A10 M48Z12 DQ7 DQ0 9 16 DQ6 DQ1 10 15 DQ5 DQ2 11 14 DQ4 DQ3 AI01187 POWER AND V PFD CIRCUITRY V CC ...

Page 7

Operation modes The M48Z02/12 also has its own Power-fail Detect circuit. The control circuitry constantly monitors the single 5V supply for an out of tolerance condition. When V tolerance, the circuit write protects the SRAM, providing a high degree ...

Page 8

... V = 4.75 to 5.5V or 4.5 to 5.5V (except where A CC from Chip Enable or t EHAX afterward. G should be kept high during WHDX WLQZ tAXQX tEHQZ tGHQZ AI01330 M48Z02/M48Z12 –150 –200 Unit Min Max Min Max 150 200 ns 150 200 ns 150 200 ...

Page 9

Figure 5. Write enable controlled, write AC waveform A0-A10 E W DQ0-DQ7 Figure 6. Chip enable controlled, write AC waveforms A0-A10 tAVEL E W DQ0-DQ7 tAVAV VALID tAVWH tAVEL tWLWH tAVWL tWLQZ DATA INPUT tDVWH tAVAV VALID tAVEH tELEH tAVWL ...

Page 10

... V = 4.75 to 5.5V or 4.5 to 5.5V (except where A CC falls within the V (max PFD to the RAM and disconnects the battery rises, the battery voltage is checked. If the voltage is too SO CC M48Z02/M48Z12 –150 –200 Unit Min Max Min Max 150 200 ...

Page 11

... In addition to transients that are caused by normal SRAM operation, power cycling can generate negative voltage spikes on V one volt. These negative spikes can cause data corruption in the SRAM while in battery backup mode. To protect from these voltage spikes, STMicroelectronics recommends connecting a schottky diode from V Schottky diode 1N5817 is recommended for through hole and MBRS120T3 is recommended for surface mount ...

Page 12

Figure 8. Supply voltage protection 12/ 0.1μF DEVICE V SS AI02169 ...

Page 13

... These are stress ratings only and operation of the device at these or any other conditions above those indicated in the Operating sections of this specification is not implied. Exposure to Absolute Maximum Rating conditions for extended periods may affect device reliability. Refer also to the STMicroelectronics SURE Program and other relevant quality documents. Table 5. ...

Page 14

... Outputs deselected. 14/20 conditions. Designers should check that the operating Parameter ) ) Grade DEVICE UNDER TEST 1kΩ includes JIG capacitance (1)(2) Parameter Table 6: M48Z02 M48Z12 4.75 to 5.5 4 100 100 ≤ 5 ≤ 1.5 1.5 5V 1.8kΩ OUT 100pF AI01019 Min ...

Page 15

Table 8. DC characteristics Symbol Parameter I Input leakage current LI (2) I Output leakage current LO I Supply current CC I Supply current (standby) TTL CC1 I Supply current (standby) CMOS CC2 V Input low voltage IL V Input ...

Page 16

... PFD CC after power 70° (min) fall time of less than tF may result in deselection/write protection not occurring passes V (min). PFD may cause corruption of RAM data. FB (1)(2) Parameter M48Z02 M48Z12 . 70° Min Max Unit 0 300 4.75 to 5.5V or 4.5 to 5.5V (except where ...

Page 17

Package mechanical data In order to meet environmental requirements, ST offers these devices in ECOPACK packages. These packages have a Lead-free second level interconnect. The category of second Level Interconnect is marked on the package and on the inner ...

Page 18

Part numbering Table 12. Ordering information scheme Example: Device type M48Z Supply voltage and write protect voltage 4.75 to 5.5V 4.5 to 5.5V Speed –70 = 70ns ...

Page 19

Revision history Table 13. Document revision history Date Revision May-1999 1.0 09-Jul-2001 2.0 17-Dec-2001 2.1 20-May-2002 2.2 01-Apr-2003 3.0 22-Apr-2003 3.1 12-Dec-2005 4.0 02-Nov-2007 First issue Reformatted; temperature information added to tables 10); Figure updated Remove ...

Page 20

... Information in this document is provided solely in connection with ST products. STMicroelectronics NV and its subsidiaries (“ST”) reserve the right to make changes, corrections, modifications or improvements, to this document, and the products and services described herein at any time, without notice. All ST products are sold pursuant to ST’s terms and conditions of sale. ...

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