CY14B104N-ZSP45XCES Cypress Semiconductor Corp, CY14B104N-ZSP45XCES Datasheet - Page 4

• Manufacturer Part Number: CY14B104N-ZSP45XCES
• Manufacturer: Cypress Semiconductor Corp
• Type: NVSRAMr

Specifications of CY14B104N-ZSP45XCES

• Word Size: 16b
• Density: 4Mb
• Interface Type: Parallel
• Access Time (max): 45ns
• Operating Supply Voltage (typ): 3.3V
• Operating Temperature Classification: Commercial
• Operating Supply Voltage (max): 3.6V
• Operating Supply Voltage (min): 2.7V
• Operating Temp Range: 0C to 70C
• Mounting: Surface Mount
• Supply Current: 50mA
• Lead Free Status / RoHS Status: Compliant

Device Operation
The CY14B104L/CY14B104N nvSRAM is made up of two
functional components paired in the same physical cell. They are
an SRAM memory cell and a nonvolatile QuantumTrap cell. The
SRAM memory cell operates as a standard fast static RAM. Data
in the SRAM is transferred to the nonvolatile cell (the STORE
operation), or from the nonvolatile cell to the SRAM (the RECALL
operation). Using this unique architecture, all cells are stored and
recalled in parallel. During the STORE and RECALL operations,
SRAM
CY14B104L/CY14B104N supports infinite reads and writes
similar to a typical SRAM. In addition, it provides infinite RECALL
operations from the nonvolatile cells and up to 200K STORE
operations.
SRAM Read
The CY14B104L/CY14B104N performs a read cycle when CE
and OE are LOW and WE and HSB are HIGH. The address
specified on pins A
data bytes or 262,144 words of 16 bits each are accessed. When
the read is initiated by an address transition, the outputs are valid
after a delay of t
or OE, the outputs are valid at t
(read cycle #2). The data output repeatedly responds to address
changes within the t
tions on any control input pins. This remains valid until another
address change or until CE or OE is brought HIGH, or WE or
HSB is brought LOW.
SRAM Write
A write cycle is performed when CE and WE are LOW and HSB
is HIGH. The address inputs must be stable before entering the
write cycle and must remain stable until CE or WE goes HIGH at
the end of the cycle. The data on the common IO pins DQ
are written into the memory if the data is valid t
of a WE controlled write or before the end of an CE controlled
write. It is recommended that OE be kept HIGH during the entire
write cycle to avoid data bus contention on common IO lines. If
OE is left LOW, internal circuitry turns off the output buffers t
after WE goes LOW.
AutoStore Operation
The CY14B104L/CY14B104N stores data to the nvSRAM using
one of the following three storage operations: Hardware Store
activated by HSB; Software Store activated by an address
sequence; AutoStore on device power down. The AutoStore
operation is a unique feature of QuantumTrap technology and is
enabled by default on the CY14B104L/CY14B104N.
During a normal operation, the device draws current from V
charge a capacitor connected to the V
charge is used by the chip to perform a single STORE operation.
If the voltage on the V
automatically disconnects the V
operation is initiated with power provided by the V
Figure 4
(V
Characteristics
Document #: 001-07102 Rev. *I
CAP
) for automatic store operation. Refer to
read
shows the proper connection of the storage capacitor
on page 7 for the size of V
and
AA
0-18
(read cycle #1). If the read is initiated by CE
AA
write
or A
access time without the need for transi-
CC
0-17
pin drops below V
operations
ACE
determines which of the 524,288
CAP
or at t
pin from V
DOE
CAP
CAP
are
, whichever is later
.
SD
SWITCH
pin. This stored
inhibited.
CC
before the end
CAP
PRELIMINARY
DC Electrical
. A STORE
, the part
capacitor.
HZWE
CC
0–15
The
to
To reduce unnecessary nonvolatile stores, AutoStore and
hardware store operations are ignored unless at least one write
operation has taken place since the most recent STORE or
RECALL cycle. Software initiated STORE cycles are performed
regardless of whether a write operation has taken place. The
HSB signal is monitored by the system to detect if an AutoStore
cycle is in progress.
Figure 4. AutoStore Mode
Hardware STORE Operation
The CY14B104L/CY14B104N provides the HSB pin to control
and acknowledge the STORE operations. Use the HSB pin to
request a hardware STORE cycle. When the HSB pin is driven
LOW, the CY14B104L/CY14B104N conditionally initiates a
STORE operation after t
begins if a write to the SRAM has taken place since the last
STORE or RECALL cycle. The HSB pin also acts as an open
drain driver that is internally driven LOW to indicate a busy
condition when the STORE (initiated by any means) is in
progress.
SRAM read and write operations that are in progress when HSB
is driven LOW by any means are given time to complete before
the STORE operation is initiated. After HSB goes LOW, the
CY14B104L/CY14B104N continues SRAM operations for
t
place. If a write is in progress when HSB is pulled low it is allowed
a time, t
requested after HSB goes LOW are inhibited until HSB returns
HIGH.
During any STORE operation, regardless of how it is initiated,
the CY14B104L/CY14B104N continues to drive the HSB pin
LOW,releasing it only when the STORE is complete.Upon
completion
CY14B104L/CY14B104N remains disabled until the HSB pin
returns HIGH. Leave the HSB unconnected if it is not used.
DELAY
. During t
DELAY
DELAY
to complete. However, any SRAM write cycles
WE
of
, multiple SRAM read operations may take
CY14B104L, CY14B104N
the
Vcc
Vcc
V
DELAY
SS
. An actual STORE cycle only
STORE
V
CAP
0.1uF
operation,
Page 4 of 23
V
CAP
the
[+] Feedback