CY14B104N-ZSP45XCES Cypress Semiconductor Corp, CY14B104N-ZSP45XCES Datasheet
CY14B104N-ZSP45XCES
Specifications of CY14B104N-ZSP45XCES
Related parts for CY14B104N-ZSP45XCES
CY14B104N-ZSP45XCES Summary of contents
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... Cypress Semiconductor Corporation Document #: 001-07102 Rev. *I PRELIMINARY 4 Mbit (512K x 8/256K x 16) nvSRAM Functional Description The Cypress CY14B104L/CY14B104N is a fast static RAM, with a nonvolatile element in each memory cell. The memory is organized as 512K words of 8 bits each or 256K words of 16 bits each. The QuantumTrap technology, producing the world’ ...
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... H NC Figure 2. Pin Diagram - 44 TSOP HSB [ DQ0 A 15 DQ1 OE DQ2 DQ7 DQ3 DQ6 DQ4 DQ5 DQ5 DQ4 DQ6 V CAP DQ7 CY14B104L, CY14B104N 48-FBGA (x16) Top View (not to scale BHE CE DQ0 DQ1 DQ2 DQ3 DQ4 SS 16 CAP DQ5 DQ6 HSB WE DQ7 ...
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... PRELIMINARY Figure 3. Pin Diagram - 54 Pin TSOP II (x16 HSB 1 [ BHE BLE 8 DQ0 46 DQ15 9 DQ1 45 DQ14 TSOP II DQ2 44 DQ13 11 (x16) 43 DQ3 DQ12 Top View not to scale) CC DQ4 40 DQ11 15 39 DQ5 DQ10 16 38 DQ6 DQ9 17 37 DQ7 DQ8 CAP Description CY14B104L, CY14B104N [2] Page [+] Feedback ...
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... Device Operation The CY14B104L/CY14B104N nvSRAM is made up of two functional components paired in the same physical cell. They are an SRAM memory cell and a nonvolatile QuantumTrap cell. The SRAM memory cell operates as a standard fast static RAM. Data in the SRAM is transferred to the nonvolatile cell (the STORE operation), or from the nonvolatile cell to the SRAM (the RECALL operation) ...
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... The six consecutive address locations must be in the order listed. WE must be HIGH during all six cycles to enable a nonvolatile cycle. 5. While there are 19 address lines on the CY14B104L/CY14B104N, only the lower 16 lines are used to control software modes state depends on the state of OE, BHE, and BLE. The IO table shown assumes OE, BHE, and BLE LOW. ...
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... AutoStore state through subsequent power down cycles. The part comes from the factory with AutoStore enabled. Data Protection The CY14B104L/CY14B104N protects data from corruption during low voltage conditions by inhibiting all externally initiated STORE and write operations. The low voltage condition is ...
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... Max, V < V < Max, V < V < Max, V < V < > – pin and Rated CAP SS CY14B104L, CY14B104N = 25°C) ................................................... 1.0W [7] .................................... 15 mA Ambient Temperature V CC 0°C to +70°C 2.7V to 3.6V –40°C to +85°C 2.7V to 3.6V Min Max Commercial Industrial – 0.2V – ...
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... OUTPUT Test Conditions Input Pulse Levels .................................................... Input Rise and Fall Times (10% - 90%) ........................ <5 ns Input and Output Timing Reference Levels .................... 1.5V Note 10. These parameters are guaranteed but not tested. Document #: 001-07102 Rev. *I PRELIMINARY CY14B104L, CY14B104N [10] Test Conditions T = 25° MHz 3.0V CC [10] ...
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... WE must be HIGH during SRAM read cycles. 12. Device is continuously selected with CE and OE both LOW. 13. Measured ±200 mV from steady state output voltage. 14 low when CE goes low, the outputs remain in the high impedance state. Document #: 001-07102 Rev. *I PRELIMINARY CY14B104L, CY14B104N Min Max Min ...
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... Description OHA DATA VALID SWITCH. Table 1 on page 5. WE must be HIGH during all six consecutive cycles. to allow read and write cycles to complete. DELAY CY14B104L, CY14B104N CY14B104L/CY14B104N Unit Min Max 2.65 V μs 150 [17, 18 Unit Min Max Min ...
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... Figure 8. SRAM Write Cycle #1: WE Controlled ADDRESS BHE , BLE DATA IN DATA OUT PREVIOUS DATA Notes 23 must be >V during address transitions. IH 24. BHE and BLE are applicable for x16 configuration only. Document #: 001-07102 Rev. *I PRELIMINARY CY14B104L, CY14B104N ACE t LZCE t DOE t LZOE t DBE t LZBE t ACTIVE ...
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... Read and Write cycles are ignored during STORE, RECALL, and while VCC is below V Document #: 001-07102 Rev. *I PRELIMINARY SCE PWE DATA VALID HIGH IMPEDANCE Figure 10. AutoStore or Power Up RECALL t STORE t HRECALL SWITCH. CY14B104L, CY14B104N [14, 22, 23, 24 [25] STORE occurs only No STORE occurs without atleast one if a SRAM write has happened SRAM write t STORE Page [+] Feedback ...
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... Switching Waveforms (continued) Figure 11. CE Controlled Software STORE/RECALL Cycle Figure 12. OE Controlled Software STORE/RECALL Cycle t RC ADDRESS # 1 ADDRESS (DATA) DATA VALID Document #: 001-07102 Rev. *I PRELIMINARY t RC ADDRESS # 6 t GHAX DATA VALID CY14B104L, CY14B104N [18] [18 STORE RECALL HIGH IMPEDANCE Page [+] Feedback ...
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... Switching Waveforms (continued) Document #: 001-07102 Rev. *I PRELIMINARY [21] Figure 13. Hardware STORE Cycle [19, 20] Figure 14. Soft Sequence Processing t SS CY14B104L, CY14B104N t SS Page [+] Feedback ...
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... TSOP II 51-85087 44-pin TSOP II 51-85128 48-ball FBGA 51-85128 48-ball FBGA 51-85128 48-ball FBGA 51-85160 54-pin TSOP II 51-85160 54-pin TSOP II 51-85160 54-pin TSOP II CY14B104L, CY14B104N Operating Range Commercial Industrial Commercial Industrial Commercial Industrial Commercial Industrial Commercial Industrial Commercial Industrial Commercial ...
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... TSOP II 51-85087 44-pin TSOP II 51-85128 48-ball FBGA 51-85128 48-ball FBGA 51-85128 48-ball FBGA 51-85160 54-pin TSOP II 51-85160 54-pin TSOP II 51-85160 54-pin TSOP II CY14B104L, CY14B104N Operating Range Commercial Industrial Industrial Commercial Commercial Industrial Commercial Industrial Commercial Industrial Commercial Industrial Commercial ...
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... Part Numbering Nomenclature 104 Pb-Free Pin Blank - 44 Pin NVSRAM 14 - Auto Store + Software Store + Hardware Store Cypress Document #: 001-07102 Rev. *I PRELIMINARY CY14B104L, CY14B104N Option Tape & Reel Blank - Std. Temperature Commercial (0 to 70° Industrial (–40 to 85°C) Package FBGA ZS - TSOP II Voltage 3.0V ...
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... Document #: 001-07102 Rev. *I PRELIMINARY Figure 15. 44-Pin TSOP II (51-85087) PIN 1 I. BASE PLANE 0°-5° 0.10 (.004) 0.597 (0.0235) 0.406 (0.0160) SEATING PLANE CY14B104L, CY14B104N DIMENSION IN MM (INCH) MAX MIN EJECTOR PIN BOTTOM VIEW 10.262 (0.404) 10.058 (0.396) ...
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... Package Diagrams (continued) Figure 16. 48-Ball FBGA - 1.2 mm (51-85128) TOP VIEW A1 CORNER 6.00±0.10 SEATING PLANE C Document #: 001-07102 Rev. *I PRELIMINARY CY14B104L, CY14B104N A BOTTOM VIEW A1 CORNER Ø0. Ø0. Ø0.30±0.05(48X 1.875 0.75 3.75 B 6.00±0.10 0.15(4X) 51-85128-*D Page [+] Feedback ...
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... Package Diagrams (continued) Document #: 001-07102 Rev. *I PRELIMINARY Figure 17. 54-Pin TSOP II (51-85160) CY14B104L, CY14B104N 51-85160-** Page [+] Feedback ...
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... Document History Page Document Title: CY14B104L/CY14B104N 4 Mbit (512K x 8/256K x 16) nvSRAM Document Number: 001-07102 Submission Orig. of Rev. ECN No. Date Change ** 431039 See ECN TUP *A 489096 See ECN TUP *B 499597 See ECN PCI *C 517793 See ECN TUP *D 774001 See ECN UHA *E 914220 ...
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... Document Title: CY14B104L/CY14B104N 4 Mbit (512K x 8/256K x 16) nvSRAM Document Number: 001-07102 Submission Orig. of Rev. ECN No. Date Change *F 1889928 See ECN vsutmp8/ AESA *G 2267286 See ECN GVCH/P YRS *H 2483627 See ECN GVCH/P YRS Document #: 001-07102 Rev. *I PRELIMINARY Description of Change Added Footnotes 1, 2 and 3. ...
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... Document Title: CY14B104L/CY14B104N 4 Mbit (512K x 8/256K x 16) nvSRAM Document Number: 001-07102 Submission Orig. of Rev. ECN No. Date Change *I 2519319 06/20/08 GVCH/P YRS Sales, Solutions, and Legal Information Worldwide Sales and Design Support Cypress maintains a worldwide network of offices, solution centers, manufacturer’s representatives, and distributors. To find the office closest to you, visit us at cypress ...