M48T513V-85CS1 STMicroelectronics, M48T513V-85CS1 Datasheet - Page 18

• Manufacturer Part Number: M48T513V-85CS1
• Manufacturer: STMicroelectronics
• Type: NVSRAMr

Specifications of M48T513V-85CS1

• Word Size: 8b
• Organization: 512x8
• Density: 4Mb
• Interface Type: Parallel
• Access Time (max): 85ns
• Operating Supply Voltage (typ): 3.3V
• Operating Temperature Classification: Commercial
• Operating Supply Voltage (max): 3.6V
• Operating Supply Voltage (min): 3V
• Operating Temp Range: 0C to 70C
• Pin Count: 32
• Mounting: Surface Mount
• Supply Current: 60mA
• Lead Free Status / RoHS Status: Supplier Unconfirmed

M48T513Y, M48T513V
Calibrating the Clock
The M48T513Y/V is driven by a quartz controlled
oscillator with a nominal frequency of 32,768Hz.
The devices are factory calibrated at 25 C and
tested for accuracy. Clock accuracy will not ex-
ceed 35 ppm (parts per million) oscillator frequen-
cy error at 25 C, which equates to about 1.53
minutes per month (see Figure 16 on page 22).
When the Calibration circuit is properly employed,
accuracy improves to better than +1/–2 ppm at
25 C. The oscillation rate of crystals changes with
temperature. The M48T513Y/V design employs
periodic counter correction. The calibration circuit
adds or subtracts counts from the oscillator divider
circuit at the divide by 256 stage, as shown in Fig-
ure Figure 17, page 22.
The number of times pulses are blanked (subtract-
ed, negative calibration) or split (added, positive
calibration) depends upon the value loaded into
the five Calibration bits found in the Control Regis-
ter. Adding counts speeds the clock up, subtract-
ing counts slows the clock down. The Calibration
bits occupy the five lower order bits (D4-D0) in the
Control Register 7FFF8h. These bits can be set to
represent any value between 0 and 31 in binary
form. Bit D5 is a Sign Bit; ’1’ indicates positive cal-
ibration, ’0’ indicates negative calibration. Calibra-
tion occurs within a 64 minute cycle. The first 62
minutes in the cycle may, once per minute, have
one second either shortened by 128 or lengthened
by 256 oscillator cycles.
If a binary ’1’ is loaded into the register, only the
first 2 minutes in the 64 minute cycle will be modi-
fied; if a binary 6 is loaded, the first 12 will be af-
fected, and so on. Therefore, each calibration step
has the effect of adding 512 or subtracting 256 os-
cillator cycles for every 125, 829, 120 actual oscil-
lator cycles, that is +4.068 or –2.034 ppm of
adjustment per calibration step in the calibration
register. Assuming that the oscillator is running at
exactly 32,768Hz, each of the 31 increments in the
Calibration byte would represent +10.7 or –5.35
seconds per month which corresponds to a total
range of +5.5 or –2.75 minutes per month. Figure
Figure 17, page 22 illustrates a TIMEKEEPER cal-
ibration waveform.
Two methods are available for ascertaining how
much calibration a given M48T513Y/V may re-
quire. The first involves setting the clock, letting it
run for a month and comparing it to a known accu-
rate reference and recording deviation over a fixed
period of time.
18/31
Calibration values, including the number of sec-
onds lost or gained in a given period, can be found
in the application note “AN934, TIMEKEEPER
CALIBRATION.”
This allows the designer to give the end user the
ability to calibrate the clock as the environment re-
quires, even if the final product is packaged in a
non-user serviceable enclosure. The designer
could provide a simple utility that accesses the
Calibration byte.
The second approach is better suited to a manu-
facturing environment, and involves the use of the
IRQ/FT pin. The pin will toggle at 512Hz, when the
Stop Bit (ST, D7 of 7FFF9h) is ’0,’ the Frequency
Test Bit (FT, D6 of 7FFFCh) is ’1,’ the Alarm Flag
Enable Bit (AFE, D7 of 7FFF6h) is ’0,’ and the
Watchdog Steering Bit (WDS, D7 of 7FFF7h) is ’1’
or the Watchdog Register (7FFF7h = 0) is reset.
Note: A 4 second settling time must be allowed
before reading the 512Hz output.
Any deviation from 512Hz indicates the degree
and direction of oscillator frequency shift at the test
temperature.
512.010124Hz would indicate a +20 ppm oscillator
frequency error, requiring a –10 (WR001010) to be
loaded into the Calibration Byte for correction.
Note that setting or changing the Calibration Byte
does not affect the Frequency test output frequen-
cy.
The IRQ/FT pin is an open drain output which re-
quires a pull-up resistor for proper operation. A
500-10k
control the rise time. The FT Bit is cleared on pow-
er-up.
Setting the Alarm Clock
Registers 7FFF6h-7FFF2h contain the alarm set-
tings. The alarm can be configured to go off at a
prescribed time on a specific year, month, date,
hour, minute, or second or repeat every month,
day, hour, minute, or second. It can also be pro-
grammed to go off while the M48T513Y/V is in the
battery back-up to serve as a system wake-up call.
Bits RPT5-RPT1 put the alarm in the repeat mode
of operation. Table 12 shows the possible config-
urations. Codes not listed in the table default to the
once per second mode to quickly alert the user of
an incorrect alarm setting.
Note: User must transition address (or toggle Chip
Enable) to see Flag Bit change.
resistor is recommended in order to
For
example,
a
reading
of