M48T513V-85CS1 STMicroelectronics, M48T513V-85CS1 Datasheet - Page 13

• Manufacturer Part Number: M48T513V-85CS1
• Manufacturer: STMicroelectronics
• Type: NVSRAMr

Specifications of M48T513V-85CS1

• Word Size: 8b
• Organization: 512x8
• Density: 4Mb
• Interface Type: Parallel
• Access Time (max): 85ns
• Operating Supply Voltage (typ): 3.3V
• Operating Temperature Classification: Commercial
• Operating Supply Voltage (max): 3.6V
• Operating Supply Voltage (min): 3V
• Operating Temp Range: 0C to 70C
• Pin Count: 32
• Mounting: Surface Mount
• Supply Current: 60mA
• Lead Free Status / RoHS Status: Supplier Unconfirmed

WRITE Mode
The M48T513Y/V is in the WRITE Mode whenever
W (WRITE Enable) and E (Chip Enable) are low
state after the address inputs are stable.
The start of a WRITE is referenced from the latter
occurring falling edge of W or E. A WRITE is termi-
nated by the earlier rising edge of W or E. The ad-
dresses must be held valid throughout the cycle. E
or W must return high for a minimum of t
Figure 10. WRITE Enable Controlled, WRITE AC Waveforms
Figure 11. Chip Enable Controlled, WRITE AC Waveforms
A0-A16
E
W
DQ0-DQ7
A0-A16
E
W
DQ0-DQ7
tAVEL
tAVEL
tAVWL
tAVWL
EHAX
tWLQZ
from
tAVWH
tWLWH
tAVAV
tAVAV
VALID
VALID
tELEH
Chip Enable or t
the initiation of another READ or WRITE cycle.
Data-in must be valid t
WRITE and remain valid for t
should be kept high during WRITE cycles to avoid
bus contention; although, if the output bus has
been activated by a low on E and G a low on W will
disable the outputs t
tDVWH
tDVWH
DATA INPUT
DATA INPUT
tWHDX
WHAX
WLQZ
tWHDX
from WRITE Enable prior to
M48T513Y, M48T513V
DVWH
tWHQX
after W falls.
tEHAX
tWHAX
WHDX
prior to the end of
AI02382
AI02582
afterward. G
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