M395T2953EZ4-CE61 Samsung Semiconductor, M395T2953EZ4-CE61 Datasheet
M395T2953EZ4-CE61
Specifications of M395T2953EZ4-CE61
Related parts for M395T2953EZ4-CE61
M395T2953EZ4-CE61 Summary of contents
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FBDIMM DDR2 Fully Buffered DIMM 240pin FBDIMMs based on 512Mb E-die INFORMATION IN THIS DOCUMENT IS PROVIDED IN RELATION TO SAMSUNG PRODUCTS, AND IS SUBJECT TO CHANGE WITHOUT NOTICE. NOTHING IN THIS DOCUMENT SHALL BE CONSTRUED AS GRANTING ANY LICENSE, ...
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... Hot-add ..................................................................................................................................13 3.6 Hot remove ..................................................................................................................................13 3.7 Hot replace 4.0 PIN CONFIGUREATION ..............................................................................................................14 5.0 FBDIMM FUNCTIONAL BLOCK DIAGRAM ...............................................................................16 5.1 512MB, 64Mx72 Module - M395T6553EZ4 5.2 1GB, 128Mx72 Module - M395T2953EZ4 5.3 2GB, 256Mx72 Module - M395T5750EZ4 6.0 ELECTRICAL CHARACTERISTICS ............................................................................................19 7.0 CHANNEL INITIALIZATION ........................................................................................................27 ..........................................................................................................5 ...............................................................................................6 .............................................................................................................7 ......................................................................................................8 ........................................................................................11 ...
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FBDIMM Revision History Revision Month Year 1.0 November 2006 1.1 January 2007 1.2 February 2007 1.3 April 2007 1.4 June 2007 1.5 October 2007 1.51 January 2008 - First Released. - Added AMB revision - Added IDT A1.5 FBD, Corrected ...
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... Table 1 : Ordering Information Part Number Density M395T6553EZ4-CD55/E65 M395T6553EZ4-CD56/E66/F76/E76 M395T6553EZ4-CD51/E61 M395T6553EZ4-CD57/E67 M395T2953EZ4-CD55/E65 M395T2953EZ4-CD56/E66/F76/E76 M395T2953EZ4-CD51/E61 M395T2953EZ4-CD57/E67 M395T5750EZ4-CD55/E65 M395T5750EZ4-CD56/E66/F76/E76 M395T5750EZ4-CD51/E61 M395T5750EZ4-CD57/E67 Note : 1. “Z” of Part number(11th digit) stands for Lead-free products. 2. The last digit stands for AMB. Table 2 : Performance range E7(DDR2-800) DDR2 DRAM Speed ...
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... FBDIMM GENERALS 2.1 FB-DIMM Operation Overview FB-DIMM (Fully Buffered Dual in Line Memory Module) is designed for the applications which require higher data transfer bandwidth and scalable memory capacity. The memory slot access rate per channel decreases as the memory bus speed increases, resulting in limited density build-up as channel speeds increase with memory system having the stub-bus architecture ...
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FBDIMM 2.2 FB-DIMM Channel Frequency Scaling There are many frequency parameters including reference clock frequency, DRAM clock frequency, DRAM data transfer rate, channel transfer rate and channel unit interval. All of frequency parameters are scaled with a certain gear ratio. ...
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FBDIMM 2.3 FB-DIMM Clocking Scheme In FB-DIMM platform design, phase adjustment among reference clock inputs to each individual AMB and host is not taken account. Thus, clock synchronization is made by using both external reference clock and channel data stream ...
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FBDIMM Figure 5 : FBDIMM Command Encoding & SB Frame Southbound Command Frame Format* Bit aE0 aE7 aE8 F0=0 aC20 aC16 aC12 aC8 aC4 aC0 1 aE1 aE6 aE9 F1=0 aC21 aC17 aC13 aC9 aC5 ...
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FBDIMM 2.6 Basic Timing Diagram Figure 7 : Basic DRAM Read Data Transfers on FBD 1 2 ACT1 FBD southbound NOP cmd/data NOP DIMM 1 cmd ACT1 DIMM 1 data DIMM 2 cmd DIMM 2 data FBD northbound data Figure ...
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FBDIMM Figure 9 : Basic DRAM Write Data Transfers on FBD ACT1 FBD southbound NOP cmd/data NOP DIMM 1 cmd ACT1 DIMM 1 data DIMM 2 cmd DIMM 2 data FBD northbound data Figure 10 : ...
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FBDIMM 2.7 Advanced Memory Buffer Block Diagram Figure 11 : Advanced Memory Buffer Block Diagram NORTH 1x2 PLL Ref Clock Reset# Reset Control Command Decoder & CRC Check Thermal Sensor Core Control and CSRs LAI Controller Data CRC Gen & ...
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FBDIMM 2.8 Interfaces Figure12 illustrates the Advanced Memory Buffer and all of its interfaces. They consist of two FBD links, one DDR2 channel and an SM- Bus interface. Each FBD link connects the Advanced Memory Buffer to a host memory ...
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FBDIMM 3.3 FBD Channel Latency FBD channel latency is measured from the time a read request is driven on the FBD channel pins to the time when the first 16 bytes (2nd chunk) of read completion data is sampled by ...
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... SS RFU = Reserved Future Use. * These pin positions are reserved for forwarded clocks to be used in future module implementations ** These pin positions are reserved for future architecture flexibility 1. The following signals are CRC bits and thus appear out of the normal sequence : PN12/PN12, SN12/SN12, PN13/PN13, SN13/SN12, PS9/PS9, SS9/SS9 ...
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... Ground SS The DNU/M_Test pin provides an external connection R/ for testing the margin of Vref which is produced by a voltage divider on the module not intended to be used in normal DNU/M_Test DNU system operation and must not be connected (DNU sys- tem. This test pin may have other features on future card de- signs and if it does, will be included in this specification at that time ...
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... FBDIMM 5.0 FBDIMM FUNCTIONAL BLOCK DIAGRAM 5.1 512MB, 64Mx72 Module - M395T6553EZ4 (populated as 1 rank of x8 DDR2 SDRAMs) S0 DQS0 DQS0 DQS9 DM/ NU/ CS DQS DQS RDQS RDQS DQ0 I/O 0 DQ1 I DQ2 I/O 2 DQ3 I/O 3 DQ4 I/O 4 DQ5 I/O 5 DQ6 I/O 6 DQ7 I/O 7 DQS1 ...
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... FBDIMM 5.2 1GB, 128Mx72 Module - M395T2953EZ4 (populated as 2 rank of x8 DDR2 SDRAMs DQS0 DQS0 DQS9 DM/ NU/ CS DQS DQS RDQS RDQS DQ0 I/O 0 DQ1 I DQ2 I/O 2 DQ3 I/O 3 DQ4 I/O 4 DQ5 I/O 5 DQ6 I/O 6 DQ7 I/O 7 DQS1 DQS1 DQS10 DM/ NU/ CS DQS DQS ...
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... FBDIMM 5.3 2GB, 256Mx72 Module - M395T5750EZ4 (populated as 2 rank of x4 DDR2 SDRAMs) VSS S1 S0 DQS0 DQS0 DM CS DQS DQS DQ0 I/O 0 DQ1 I DQ2 I/O 2 DQ3 I/O 3 DQS1 DQS1 DM CS DQS DQS DQ8 I/O 0 DQ9 I DQ10 I/O 2 DQ11 I/O 3 DQS2 DQS2 DM CS DQS DQS ...
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FBDIMM 6.0 ELECTRICAL CHARACTERISTICS Table 6 : AbsoIute Maximum Ratings Parameter Voltage on any pin relative Voltage on V pin relative Voltage V pin relative Voltage on V pin ...
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FBDIMM Table 9 : Power specification parameter and test condition Symbol Icc_Idle_0 Idle Current, single or last DIMM L0 state, idle (0 BW) Primary channel enabled, Secondary Channel Disabled Idd_Idle_0 CKE high. Command and address lines stable. DRAM clock active. ...
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... D57 E65 E66/E61 (PC2-5300) 2090 2600 2600 666 1330 1330 4.557 6.622 6.622 2930 3400 3400 666 1330 1330 5 ...
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FBDIMM Table 10-3 : Power specification (Vdd Max = 1.900V, Vcc Max = 1.575V) Symbol D55 D56/D51 (PC2-4200) Icc_Idle_0 2200 2200 Idd_Idle_0 1980 1980 P_idle_0 7.227 7.227 Icc_Idle_1 3000 3000 Idd_Idle_1 1980 1980 P_idle_1 8.487 8.487 Icc_active_1 3400 3400 Idd_active_1 ...
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FBDIMM Table Currents TT Description Idle current, DDR2 SDRAM device power down Active power, 50% DDR2 SDRAM BW Table 12 : Reference Clock Input Specifications Parameter Reference clock frequency @3.2 Gb/s (nominal 133.33 MHz) Reference clock frequency ...
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FBDIMM Table 13 : Differential Transmitter Output Specifications Parameter Differential peak-to-peak output voltage for large voltage swing Differential peak-to -peak output voltage for requ- lar voltage swing Differential peak-to-peak output voltage for small votage swing DC common code output voltage ...
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FBDIMM Table 14 : Differential Receiver Input Specifications Parameter Differential peak-to-peak input voltage for large volt- age swing Maximum single-ended voltage in El condition Maximum single-ended voltage in Ei condition (DC only) Maximum peak-to-peak differential voltage in El condition Single-ended ...
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FBDIMM 11. The received differential signal must satisfy both this ratio as well as the absolute maximum AC peaktopeak common mode specification. For example, if VRX-DIFFp-p is 200 mV, the maximum AC peak-to peak common mode is the lesser of ...
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FBDIMM 7.0 CHANNEL INITIALIZATION This chapter defines the process of initializing the FBD channel. The FBD initialzation process generally follows the top to bottom se- quence of state transitions shown in the high level AMB Initialization Flow diagram in Figure ...
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... FBDIMM Figure 17 : FBDIMM Physical Dimension -1 (For PCB) : 64Mbx8 based 64Mx72 Module (1Rank DIA. 2.0 +0.1/-0 67 5.175 5.0 0.8 +/- 0.05 2.50 2.50 3.80 MAX 0.178 1.50 DETAIL a M395T6553EZ4 133.35 126.85 d AMB 123 R0.75 120° 1.25 1.00 DETAIL b DETAIL DDR2 SDRAM 2x 2 ...
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... FBDIMM Figure 18 : FBDIMM Physical Dimension -2 (For Heat Spreader): 64Mbx8 based 64Mx72 Module (1Rank) 67 M395T6553EZ4 133.35 51 123 DDR2 SDRAM Units : Millimeters 8.2 max 1.27 ± 0.10 Back 3.0 max Rev. 1.51 January 2008 ...
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... FBDIMM Figure 19 : FBDIMM Physical Dimension -1 (For PCB) : 64Mbx8 based 128Mx72 Module (2Rank DIA. 2.0 +0.1/-0 67 5.175 5.0 0.8 +/- 0.05 2.50 2.50 3.80 MAX 0.178 1.50 DETAIL a M395T2953EZ4 133.35 126.85 d AMB 123 R0.75 120° 1.25 1.00 DETAIL b DETAIL DDR2 SDRAM 2x 2 ...
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... FBDIMM Figure 20 : FBDIMM Physical Dimension -2 (For Heat Spreader) : 64Mbx8 based 128Mx72 Module (2Rank) 67 M395T2953EZ4 133.35 51 123 DDR2 SDRAM Units : Millimeters 8.2 max 1.27 ± 0.10 Back 3.0 max Rev. 1.51 January 2008 ...
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... FBDIMM Figure 21 : FBDIMM Physical Dimension -1 (For PCB) : 128Mbx4 based 256Mx72 Module (2Rank DIA. 2.0 +0.1/-0 67 5.175 5.0 0.8 +/- 0.05 2.50 2.50 3.80 MAX 0.178 1.50 DETAIL a M395T5750EZ4 133.35 126.85 d AMB 123 R0.75 120° 1.25 1.00 DETAIL b DETAIL DDR2 SDRAM 2x 2 ...
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... FBDIMM Figure 22 : FBDIMM Physical Dimension -2 (For Heat Spreader) : 128Mbx4 based 256Mx72 Module (2Rank) 67 M395T5750EZ4 133.35 51 123 DDR2 SDRAM Units : Millimeters 8.2 max 1.27 ± 0.10 Back 3.0 max Rev. 1.51 January 2008 ...