SAA4956TJ/V2,512 NXP Semiconductors, SAA4956TJ/V2,512 Datasheet - Page 8

• Manufacturer Part Number: SAA4956TJ/V2,512
• Manufacturer: NXP Semiconductors

Specifications of SAA4956TJ/V2,512

• Operating Temperature (max): 70C
• Operating Temperature (min): 0C
• Mounting: Surface Mount
• Operating Temperature Classification: Commercial
• Lead Free Status / RoHS Status: Compliant

Philips Semiconductors
During this time, control signals WE and IE will function as
defined for normal operation. The remaining 12 bits of the
13-bit write block address must be applied, in turn, to the
selected input pin (D0 or IE) at the following 12 positive
transitions of SWCK. The Least Significant Bit (LSB) of the
write block address is applied at the 17th positive
transition of SWCK. A write latency period of 18 additional
SWCK clock cycles is required before write access to the
new block address is possible. During this time, data is
transferred from the serial write and parallel write registers
into the memory array and the write pointer is set to the
new block address.
Block address values between 0 and 6143 are valid.
Values outside this range must be avoided because invalid
block addresses can result in abnormal operation or a
lock-up condition. Recovery from lock-up requires a
standard reset write operation.
WE must remain LOW from the 3rd positive transition of
SWCK to the 17th write latency SWCK clock cycle if the
block address is applied to pin D0. If the block address is
applied to pin IE, WE must be HIGH on the 5th positive
transition of SWCK, may be HIGH or LOW on the
6th transition, and must be LOW from the 7th transition to
the 17th write latency SWCK clock cycle.
At the 18th write latency SWCK clock cycle, IE and WE
may be switched HIGH to prepare for writing new data at
the next positive transition of SWCK. The complete write
block access entry sequence is finished after the
18th write latency cycle.
The LOW-to-HIGH transition on RSTW required at the
beginning of the sequence should not be repeated.
Additional LOW-to-HIGH transitions on RSTW would
disable write block address mode and reset the write
pointer.
7.1.1.3
Two different types of memory are used in the data
address area: a mini cache for the first 12 data words after
a reset write or a reset read, and a DRAM cell memory
array with a 245760 word capacity. Each word is 12 bits
long. The mini cache is needed to store data temporarily
after a reset operation since a latency period is required
before read or write access to the memory array is
possible. Latency periods are needed for read or write
operations in random read or write block access modes
because data is read from, or written to, the memory array.
The data in the mini cache can only be accessed directly
after a standard reset operation. It cannot be accessed in
random read or write block access modes.
1998 Dec 08
2.9-Mbit field memory with noise reduction
Address organization
8
The address area reserved for the mini cache, accessible
after a standard reset operation, is from decimal 12 to 1.
The memory array starts at decimal 0 and ends at 245759.
Decimal address 0 is identical to block address 0000H.
Because a single block address is defined for every
40 words in the memory array, block address 0001H
corresponds to decimal address 40. The highest block
address is 17FFH. This block has a decimal start address
of 245720 and an end address of 245759.
If a read or write reset operation is not performed, the next
read or write pointer address after 245759 will be
address 0 due to pointer wraparound. It should be noted
that reset read and write operations should occur together.
If one pointer wraps around while the other is reset, either
12 words will be lost or 12 words of undefined data will be
read.
7.1.1.4
A positive transition on the SWCK write clock latches the
data on inputs D0 to D11, provided WE was HIGH at the
previous positive transition of SWCK. The data input
set-up (t
positive transition of SWCK (see Fig.5). The latched data
will only be written into memory if IE was HIGH at the
previous positive transition of SWCK.
7.1.1.5
Pin WE is used to enable or disable a data write operation.
The WE signal controls data inputs D0 to D11. In addition,
the internal write address pointer is incremented if WE is
HIGH at the positive transition of the SWCK write clock.
WE set-up (t
to the positive edge of SWCK (see Fig.8).
7.1.1.6
Pin IE is used to enable or disable a data write operation
from the D0 to D11 data inputs into memory. The latched
data will only be written into memory if the IE and WE
signals were HIGH during the previous positive transition
of SWCK. A LOW level on IE will prevent the data being
written into memory and existing data will not be
overwritten (write mask function; see Fig.10). The IE
set-up (t
positive edge of SWCK (see Fig.9).
su(D)
su(IE)
Data inputs: D0 to D11 and write clock: SWCK
Write enable: WE
Input enable: IE
) and hold (t
su(WE)
) and hold (t
) and hold (t
h(D)
h(IE)
) times are referenced to the
) times are referenced to the
h(WE)
Preliminary specification
) times are referenced
SAA4956TJ