5962-8606308YA QP SEMICONDUCTOR, 5962-8606308YA Datasheet - Page 3

• Manufacturer Part Number: 5962-8606308YA
• Manufacturer: QP SEMICONDUCTOR

Specifications of 5962-8606308YA

• Organization: 32Kx8
• Interface Type: Parallel
• In System Programmable: External
• Access Time (max): 70ns
• Package Type: LCC
• Reprogramming Technique: OTP
• Operating Supply Voltage (typ): 5V
• Operating Supply Voltage (min): 4.5V
• Operating Supply Voltage (max): 5.5V
• Supply Current: 60mA
• Pin Count: 32
• Mounting: Surface Mount
• Operating Temp Range: -55C to 125C
• Operating Temperature Classification: Military
• Lead Free Status / RoHS Status: Not Compliant

Upon delivery, or after each erasure, the device has all of its bits in the “ONE”, or HIGH state. “ZEROs” are loaded into
the device through the programming procedure.
The device enters the programming mode when 12.75V ± 0.25V is applied to the V
are at V
For programming, the data to be programmed is applied 8 bits in parallel to the data pins.
The programming algorithm uses a 100 μs programming pulse and gives each address only as many pulses as needed
to reliably program the data. After each pulse is applied to a given address, the data in that address is verified. If the
data does not verify, additional pulses are given until it verifies or the maximum pulses allowed is reached. This process
is repeated while sequencing through each address of the device. This part of the algorithm is done with V
assure that each bit is programmed to a sufficiently high threshold voltage. After the final address is completed, the
entire EPROM memory is verified at V
Program Inhibit
Programming different data to multiple devices in parallel is easily accomplished. Except for
devices may be common. A TTL low-level program pulse applied to one device’s
and
programmed.
Program Verify
Verification should be performed on the programmed bits to determine that they were correctly programmed. Verify
should be performed with
Autoselect Mode
The autoselect mode provides manufacturer and device identification through identifier codes on DQ0–DQ7. This mode
is primarily intended for programming equipment to automatically match a device to be programmed with its
corresponding programming algorithm. This mode is functional in the 25°C ± 5°C ambient temperature range that is
required when programming the device. To activate this mode, the programming equipment must force V
line A9. Two identifier bytes may then be sequenced from the device outputs by toggling address line A0 from V
(that is, changing the address from 00h to 01h). All other address lines must be held at V
Byte 0 (A0 = V
odd parity, with DQ7 as the parity bit.
Read Mode
To obtain data at the device outputs, Chip Enable (
power to the device and is typically used to select the device.
device selection. Addresses must be stable for at least t
Standby Mode
The device enters the CMOS standby mode when
The device enters the TTL-standby mode when
either standby mode, the device places its outputs in a high-impedance state, independent of the
Output OR Connection
To accommodate multiple memory connections, a two-line control function provides:
to all devices in the array and connected to the READ line from the system control bus. This assures that all deselected
memory devices are in their low-power standby mode and that the output pins are only active when data is desired from
a particular memory device.
System Applications
During the switch between active and standby conditions, transient current peaks are produced on the rising and falling
edges of Chip Enable. The magnitude of these transient current peaks is dependent on the output capacitance loading
of the device. As a minimum, a 0.1μF ceramic capacitor (high frequency, low inductance) should be used on each
device between V
inductive effects of the printed circuit board traces on EPROM arrays, a 4.7μF bulk electrolytic capacitor should be used
CE
•
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QP SEMI, 2945 Oakmead Village Court, Santa Clara, CA 95051
should be decoded and used as the primary device selecting function, while
OE
IL
Low memory power dissipation
Assurance that output bus contention will not occur.
HIGH will program that particular device. A high-level
.
IL
) represents the manufacturer code, and Byte 1 (A0 = V
CC
and V
SS
OE
to minimize transient effects. In addition, to overcome the voltage drop caused by the
at V
IL
,
CC
CE
= V
at V
PP
IH
= 5.25 V.
CE
and V
CE
CE
is at V
PP
) and Output Enable (
is at V
ACC
between 12.5 V and 13.0 V.
–t
IH
. Maximum VCC current is reduced to 1.0 mA. When in
OE
CC
OE
.
CE
± 0.3 V. Maximum V
enables the device to output data, independent of
input inhibits the other devices from being
IH
), the device identifier code. Both codes have
OE
) must be driven low.
CE
OE
PP
CC
pin, and both
input with V
be made a common connection
current is reduced to 100 μA.
QP27C256 & QP27C256L
IL
during the autoselect mode.
CE
, all like inputs of the
PP
OE
OE
= 12.75 V ± 0.25 V
input.
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CE
is at V
H
CC
on address
controls the
= 6.25 V to
IH
IL
&
to V
CE
IH