K4S281632FUC75 Samsung Semiconductor, K4S281632FUC75 Datasheet - Page 6

• Manufacturer Part Number: K4S281632FUC75
• Manufacturer: Samsung Semiconductor
• Type: SDRAMr

Specifications of K4S281632FUC75

• Organization: 8Mx16
• Density: 128Mb
• Address Bus: 14b
• Access Time (max): 6/5.4ns
• Maximum Clock Rate: 166MHz
• Operating Supply Voltage (typ): 3.3V
• Package Type: TSOP-II
• Operating Temp Range: 0C to 70C
• Operating Supply Voltage (max): 3.6V
• Operating Supply Voltage (min): 3V
• Supply Current: 140mA
• Pin Count: 54
• Mounting: Surface Mount
• Operating Temperature Classification: Commercial
• Lead Free Status / RoHS Status: Compliant

PIN CONFIGURATION (Top view)
SDRAM 128Mb F-die (x4, x8, x16)
PIN FUNCTION DESCRIPTION
CLK
CS
CKE
A
BA
RAS
CAS
WE
DQM
DQ
V
V
N.C/RFU
0
DD
DDQ
~ A
0
0
/V
~ BA
~
Pin
/V
SS
11
N
SSQ
1
System clock
Chip select
Clock enable
Address
Bank select address
Row address strobe
Column address strobe
Write enable
Data input/output mask
Data input/output
Power supply/ground
Data output power/ground
No connection
/reserved for future use
A10/AP
LDQM
x16
V
V
V
V
DQ0
DQ1
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7
CAS
RAS
BA0
BA1
V
V
V
DDQ
DDQ
SSQ
SSQ
WE
CS
A0
A1
A2
A3
DD
DD
DD
Name
A10/AP
x8
V
V
V
V
DQ0
DQ1
DQ2
DQ3
CAS
RAS
BA0
BA1
V
V
V
DDQ
N.C
N.C
DDQ
N.C
N.C
N.C
SSQ
SSQ
WE
CS
A0
A1
A2
A3
DD
DD
DD
A10/AP
x4
V
V
V
V
DQ0
DQ1
CAS
RAS
BA0
BA1
V
V
V
N.C
DDQ
N.C
N.C
N.C
DDQ
N.C
N.C
N.C
SSQ
SSQ
WE
CS
A0
A1
A2
A3
DD
DD
DD
Active on the positive going edge to sample all inputs.
Disables or enables device operation by masking or enabling all inputs except
CLK, CKE and DQM
Masks system clock to freeze operation from the next clock cycle.
CKE should be enabled at least one cycle prior to new command.
Disable input buffers for power down in standby.
Row/column addresses are multiplexed on the same pins.
Row address : RA
Column address : (x4 : CA
Selects bank to be activated during row address latch time.
Selects bank for read/write during column address latch time.
Latches row addresses on the positive going edge of the CLK with RAS low.
Enables row access & precharge.
Latches column addresses on the positive going edge of the CLK with CAS low.
Enables column access.
Enables write operation and row precharge.
Latches data in starting from CAS, WE active.
Makes data output Hi-Z, t
Blocks data input when DQM active.
Data inputs/outputs are multiplexed on the same pins.
(x4 : DQ
Power and ground for the input buffers and the core logic.
Isolated power supply and ground for the output buffers to provide improved noise
immunity.
This pin is recommended to be left No Connection on the device.
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
0
~
3
),
(x8 : DQ
0
~ RA
54
53
52
51
50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
11
SHZ
0
0
V
N.C
V
N.C
DQ3
V
N.C
N.C
V
N.C
DQ2
V
N.C
V
N.C/RFU
DQM
CLK
CKE
N.C
A11
A9
A8
A7
A6
A5
A4
V
,
~
SS
SSQ
DDQ
SSQ
DDQ
SS
SS
~ CA
x4
7
after the clock and masks the output.
),
9
(x16 : DQ
,CA
Input Function
V
DQ7
V
N.C
DQ6
V
N.C
DQ5
V
N.C
DQ4
V
N.C
V
N.C/RFU
DQM
CLK
CKE
N.C
A11
A9
A8
A7
A6
A5
A4
V
11
SS
SSQ
DDQ
SSQ
DDQ
SS
SS
x8
), (x8 : CA
0
~
15
V
DQ15
V
DQ14
DQ13
V
DQ12
DQ11
V
DQ10
DQ9
V
DQ8
V
N.C/RFU
UDQM
CLK
CKE
N.C
A11
A9
A8
A7
A6
A5
A4
V
)
x16
SS
SSQ
DDQ
SSQ
DDQ
SS
SS
0
~ CA
Rev. 1.2 August 2004
9
), (x16 : CA
CMOS SDRAM
(0.8 mm Pin pitch)
(400mil x 875mil)
54Pin TSOP
0
~ CA
8
)