K4S281632FUC75 Samsung Semiconductor, K4S281632FUC75 Datasheet

no-image

K4S281632FUC75

Manufacturer Part Number
K4S281632FUC75
Description
Manufacturer
Samsung Semiconductor
Type
SDRAMr
Datasheet

Specifications of K4S281632FUC75

Organization
8Mx16
Density
128Mb
Address Bus
14b
Access Time (max)
6/5.4ns
Maximum Clock Rate
166MHz
Operating Supply Voltage (typ)
3.3V
Package Type
TSOP-II
Operating Temp Range
0C to 70C
Operating Supply Voltage (max)
3.6V
Operating Supply Voltage (min)
3V
Supply Current
140mA
Pin Count
54
Mounting
Surface Mount
Operating Temperature Classification
Commercial
Lead Free Status / RoHS Status
Compliant
SDRAM 128Mb F-die (x4, x8, x16)
CMOS SDRAM
128Mb F-die SDRAM Specification
54 TSOP-II with Pb-Free
(RoHS compliant)
Revision 1.2
August 2004
* Samsung Electronics reserves the right to change products or specification without notice.
Rev. 1.2 August 2004

Related parts for K4S281632FUC75

K4S281632FUC75 Summary of contents

Page 1

... SDRAM 128Mb F-die (x4, x8, x16) 128Mb F-die SDRAM Specification 54 TSOP-II with Pb-Free * Samsung Electronics reserves the right to change products or specification without notice. (RoHS compliant) Revision 1.2 August 2004 CMOS SDRAM Rev. 1.2 August 2004 ...

Page 2

... SDRAM 128Mb F-die (x4, x8, x16) Revision History Revision 1.0 (January, 2004) - First release. Revision 1.1 (May, 2004) • Added Note 5. sentense of tRDL parameter. Revision 1.2 (August, 2004) • Corrected typo. CMOS SDRAM Rev. 1.2 August 2004 ...

Page 3

... SDRAM 128Mb F-die (x4, x8, x16 4Bit x 4 Banks / 4M x 8Bit x 4 Banks / 2M x 16Bit x 4 Banks SDRAM FEATURES • JEDEC standard 3.3V power supply • LVTTL compatible with multiplexed address • Four banks operation • MRS cycle with address key programs -. CAS latency (2 & ...

Page 4

... SDRAM 128Mb F-die (x4, x8, x16) Package Physical Dimension #54 #1 0.10 MAX 0.004 0. 0.028 #28 #27 22.62 MAX 0.891 22.22 ± 0.10 ± 0.004 0.875 0.008 +0.10 0.30 0.80 -0.05 +0.004 0.0315 0.012 -0.002 54Pin TSOP Package Dimension CMOS SDRAM 0~8°C 0.25 TYP 0 ...

Page 5

... SDRAM 128Mb F-die (x4, x8, x16) FUNCTIONAL BLOCK DIAGRAM Bank Select CLK ADD LCKE LRAS LCBR CLK CKE * Samsung Electronics reserves the right to change products or specification without notice. Data Input Register Column Decoder Latency & Burst Length Programming Register LWE LCAS Timing Register ...

Page 6

... SDRAM 128Mb F-die (x4, x8, x16) PIN CONFIGURATION (Top view) x8 x16 DQ0 DQ0 V V DDQ DDQ DQ1 N.C DQ2 DQ1 V V SSQ SSQ DQ3 N.C DQ4 DQ2 V V DDQ DDQ DQ5 N.C DQ6 DQ3 V V SSQ SSQ DQ7 N LDQM N CAS CAS RAS ...

Page 7

... SDRAM 128Mb F-die (x4, x8, x16) ABSOLUTE MAXIMUM RATINGS Parameter Voltage on any pin relative to Vss Voltage on V supply relative to Vss DD Storage temperature Power dissipation Short circuit current Note : Permanent device damage may occur if "ABSOLUTE MAXIMUM RATINGS" are exceeded. Functional operation should be restricted to recommended operating condition. ...

Page 8

... SDRAM 128Mb F-die (x4, x8, x16) DC CHARACTERISTICS (x4, x8) (Recommended operating condition unless otherwise noted, T Parameter Symbol Operating current I CC1 (One bank active) I CC2 Precharge standby current in PS CKE & CLK ≤ V power-down mode I CC2 I CC2 Precharge standby current in non power-down mode I NS ...

Page 9

... SDRAM 128Mb F-die (x4, x8, x16) DC CHARACTERISTICS (x16) (Recommended operating condition unless otherwise noted, T Parameter Symbol Operating current I CC1 (One bank active) I CC2 Precharge standby current in PS CKE & CLK ≤ V power-down mode I CC2 I CC2 Precharge standby current in non power-down mode I NS ...

Page 10

... SDRAM 128Mb F-die (x4, x8, x16) AC OPERATING TEST CONDITIONS Parameter Input levels (Vih/Vil) Input timing measurement reference level Input rise and fall time Output timing measurement reference level Output load condition Output 870Ω (Fig output load circuit OPERATING AC PARAMETER (AC operating conditions unless otherwise noted) ...

Page 11

... SDRAM 128Mb F-die (x4, x8, x16) AC CHARACTERISTICS (AC operating conditions unless otherwise noted) Parameter Symbol CAS latency=3 CLK cycle time CAS latency=2 CAS latency=3 CLK to valid output delay CAS latency=2 CAS latency=3 Output data hold time CAS latency=2 CLK high pulse width CLK low pulse width ...

Page 12

... SDRAM 128Mb F-die (x4, x8, x16) IBIS SPECIFICATION I Characteristics (Pull-up) OH 100MHz 100MHz Voltage 133MHz 133MHz Min Max (V) I (mA) I (mA) 3.45 -2.4 3.3 -27.3 3.0 0.0 -74.1 2.6 -21.1 -129.2 2.4 -34.1 -153.3 2.0 -58.7 -197.0 1.8 -67.3 -226.2 1.65 -73.0 -248.0 1.5 -77 ...

Page 13

... SDRAM 128Mb F-die (x4, x8, x16) V Clamp @ CLK, CKE, CS, DQM & (V) I (mA) DD 0.0 0.0 0.2 0.0 0.4 0.0 0.6 0.0 0.7 0.0 0.8 0.0 0.9 0.0 1.0 0.23 1.2 1.34 1.4 3.02 1.6 5.06 1.8 7.35 2.0 9.83 2.2 12.48 2.4 15 ...

Page 14

... MRS can be issued only at all banks precharge state. A new command can be issued after 2 CLK cycles of MRS. 3. Auto refresh functions are as same as CBR refresh of DRAM. The automatical precharge without row precharge command is meant by "Auto". Auto/self refresh can be issued only at all banks precharge state. ...

Related keywords