LAN9500I-ABZJ Standard Microsystems (SMSC), LAN9500I-ABZJ Datasheet - Page 14

• Manufacturer Part Number: LAN9500I-ABZJ
• Manufacturer: Standard Microsystems (SMSC)

Specifications of LAN9500I-ABZJ

• Operating Temperature (min): -40C
• Operating Temperature Classification: Industrial
• Operating Temperature (max): 85C
• Rad Hardened: No
• Lead Free Status / RoHS Status: Compliant

Revision 1.0 (05-17-10)
NUM PINS
1
1
1
Purpose I/O 2
Transmit Data
Purpose I/O 7
Transmit Data
Purpose I/O 6
(Internal PHY
(Internal PHY
(Internal PHY
Management
Configuration
Configuration
PHY Mode)
Mode Only)
PHY Mode)
Mode Only)
PHY Mode)
Mode Only)
EEPROM
USB Port
(External
(External
(External
General
General
General
NAME
Clock
Swap
Strap
Strap
Size
3
2
PORT_SWAP
EEP_SIZE
SYMBOL
Table 3.1 MII Interface Pins (continued)
GPIO2
GPIO7
GPIO6
TXD3
TXD2
MDC
DATASHEET
BUFFER
IS/O8/
IS/O8/
IS/O8/
TYPE
(PD)
OD8
(PU)
(PU)
OD8
(PU)
(PU)
(PD)
OD8
(PU)
(PD)
O8
O8
O8
IS
IS
14
In external PHY mode, this pin outputs the
management clock to the external PHY.
This General Purpose I/O pin is fully
programmable as either a push-pull output, an
open-drain output, or a Schmitt-triggered input.
In external PHY mode, this pin functions as the
transmit data 3 output to the external PHY.
This General Purpose I/O pin is fully
programmable as either a push-pull output, an
open-drain output, or a Schmitt-triggered input.
Note:
The EEP_SIZE strap selects the size of the
EEPROM attached to the device.
0 = 128 byte EEPROM is attached and a total of
seven address bits are used.
1 = 256/512 byte EEPROM is attached and a
total of nine address bits are used.
Note:
See
configuration straps.
In external PHY mode, this pin functions as the
transmit data 2 output to the external PHY.
This General Purpose I/O pin is fully
programmable as either a push-pull output, an
open-drain output, or a Schmitt-triggered input.
Swaps the mapping of USBDP and USBDM.
0 = USBDP maps to the USB D+ line and
USBDM maps to the USB D- line.
1 = USBDP maps to the USB D- line. USBDM
maps to the USB D+ line.
See
configuration straps.
Note 3.1
Note 3.1
(LAN9500A/LAN9500Ai ONLY):
GPIO7 may provide additional PHY Link
Up related functionality.
A 3-wire style 1K/2K/4K EEPROM that
is organized for 128 x 8-bit or 256/512 x
8-bit operation must be used.
for more information on
for more information on
DESCRIPTION
USB 2.0 to 10/100 Ethernet Controller
SMSC LAN950x Family
Datasheet