LAN9500I-ABZJ Standard Microsystems (SMSC), LAN9500I-ABZJ Datasheet
LAN9500I-ABZJ
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LAN9500I-ABZJ Summary of contents
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... Automatic payload padding and pad removal — Loop-back modes — TCP/UDP/IP/ICMP checksum offload support 1 = LAN9500A/LAN9500Ai only SMSC LAN950x Family LAN9500/LAN9500i LAN9500A/LAN9500Ai USB 2.0 to 10/100 Ethernet Controller — Flexible address filtering modes – One 48-bit perfect address – 64 hash-filtered multicast addresses – ...
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... LAN9500-ABZJ for 56-pin, QFN lead-free RoHS compliant package (0 to +70°C temp range) LAN9500i-ABZJ for 56-pin, QFN lead-free RoHS compliant package (-40 to +85°C temp range) LAN9500A-ABZJ for 56-pin, QFN lead-free RoHS compliant package (0 to +70°C temp range) LAN9500Ai-ABZJ for 56-pin, QFN lead-free RoHS compliant package (-40 to +85°C temp range) ...
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... Chapter 5 EEPROM Controller (EPC 5.1 EEPROM Format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 5.2 EEPROM Defaults . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 5.3 EEPROM Auto-Load 5.4 Examples of EEPROM Format Interpretation 5.4.1 LAN9500/LAN9500i . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 5.4.2 LAN9500A/LAN9500Ai . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 5.5 Customized Operation Without EEPROM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 Chapter 6 PME Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 Chapter 7 NetDetach Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44 Chapter 8 Operational Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46 8.1 Absolute Maximum Ratings 8.2 Operating Conditions** ...
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Chapter 9 Package Outline . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...
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USB 2.0 to 10/100 Ethernet Controller Datasheet List of Figures Figure 1.1 System Component Differences . . . . . . . . . . . . . . . . . . . . . . . . . ...
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... Table 5.2 Configuration Flags . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 Table 5.3 GPIO PME Flags . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 Table 5.4 EEPROM Defaults . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 Table 5.5 Dump of EEPROM Memory - LAN9500/LAN9500i . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 Table 5.6 EEPROM Example - 256 Byte EEPROM - LAN9500/LAN9500i . . . . . . . . . . . . . . . . . . . . . . . 31 Table 5.7 Dump of EEPROM Memory - LAN9500A/LAN9500Ai Table 5.8 EEPROM Example - 256 Byte EEPROM - LAN9500A/LAN9500Ai . . . . . . . . . . . . . . . . . . . . 36 Table 8 ...
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... X X LAN9500Ai X X The LAN9500/LAN9500i and LAN9500A/LAN9500Ai are pin compatible. However, the value of the required EXRES resistor and other system components differ between devices. Refer to the LAN950x reference schematics for additional information. SMSC LAN950x Family Table 1.1 provides a summary of the feature differences between family Table 1 ...
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... For LAN9500A/LAN9500Ai: 0 Ohm 49.9 49.9 49.9 49.9 Ohm Ohm Ohm Ohm Ethernet Magnetics/RJ45 R2 For LAN9500/LAN9500i: 12.4K Ohm 1% For LAN9500A/LAN9500Ai: 12.0K Ohm 1% For LAN9500/LAN9500i: 1M Ohm 1% For LAN9500A/LAN9500Ai: Do Not Populate R3 25.000MHz 33pF 33pF 8 DATASHEET USB 2.0 to 10/100 Ethernet Controller Datasheet To Ethernet SMSC LAN950x Family ...
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USB 2.0 to 10/100 Ethernet Controller Datasheet Chapter 2 Introduction 2.1 Block Diagram USB 2.0 USB USB Device PHY Controller TAP JTAG Controller LAN950x 2.1.1 Overview The LAN950x is a high performance Hi-Speed USB 2.0 to 10/100 Ethernet controller. With ...
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... PHY. This option allows support for HomePNA and HomePlug applications. The Ethernet MAC/PHY supports numerous power management wakeup features, including “Magic Packet”, “Wake on LAN”, and “Link Status Change”. Eight wakeup frame filters are provided by LAN9500A/LAN9500Ai, while LAN9500/LAN9500i support four. 2.1.5 Power Management The LAN950x features four SUSPEND2, and SUSPEND3 ...
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USB 2.0 to 10/100 Ethernet Controller Datasheet 2.1.6 EEPROM Controller The LAN950x contains an EEPROM controller for connection to an external EEPROM. This allows for the automatic loading of static configuration data upon power-on reset, pin reset, or software reset. ...
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... TXD0/GPIO4/EEP_DISABLE 56 Note: ** This pin is a no-connect (NC) for LAN9500A/LAN9500Ai, but may be connected to VDD33A for backward compatibility with LAN9500/LAN9500i. Note: *** For LAN9500A/LAN9500Ai this pin provides additional PME related functionality. Refer to the respective pin descriptions and information. Note: **** For LAN9500A/LAN9500Ai GPIO7 may provide additional PHY Link Up related functionality ...
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USB 2.0 to 10/100 Ethernet Controller Datasheet NUM PINS NAME Receive Error (External 1 PHY Mode) Transmit Enable 1 (External PHY Mode) Receive Data Valid 1 (External PHY Mode) Receive Clock 1 (External PHY Mode) Carrier Sense (External PHY Mode) ...
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NUM PINS NAME Management Clock (External PHY Mode) 1 General Purpose I/O 2 (Internal PHY Mode Only) Transmit Data 3 (External PHY Mode) General Purpose I/O 7 (Internal PHY Mode Only) EEPROM 1 Size Configuration Strap Transmit Data 2 (External ...
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USB 2.0 to 10/100 Ethernet Controller Datasheet NUM PINS NAME Transmit Data 1 (External PHY Mode) General Purpose I/O 5 (Internal PHY Mode Only) 1 Remote RMT_WKP Wakeup Configuration Strap Transmit Data 0 (External PHY Mode) General Purpose I/O 4 ...
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NUM PINS NAME EEPROM 1 Data In EEPROM Data Out Auto-MDIX AUTOMDIX_EN Enable Configuration Strap 1 EEPROM Chip Select 1 EEPROM Clock Power Select Configuration 1 Strap Note 3.2 Configuration strap values are latched on power-on reset and system reset. ...
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USB 2.0 to 10/100 Ethernet Controller Datasheet NUM PINS NAME JTAG Test Port Reset (Internal PHY Mode) 1 Receive Data 0 (External PHY Mode) JTAG Test Data Out (Internal PHY Mode) 1 PHY Reset nPHY_RST (External PHY Mode) JTAG Test ...
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NUM PINS NAME PHY Select 1 System Reset 1 Ethernet nFDX_LED Full-Duplex Indicator LED General Purpose I Ethernet Link nLNKA_LED Activity Indicator LED General Purpose I Revision 1.0 (05-17-10) Table 3.4 Miscellaneous Pins BUFFER SYMBOL TYPE ...
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USB 2.0 to 10/100 Ethernet Controller Datasheet NUM PINS NAME Ethernet nSPD_LED Speed Indicator LED General Purpose I Detect VBUS_DET Upstream VBUS Power 1 Test 1 1 Test 2 1 Test 3 1 SMSC LAN950x Family Table 3.4 ...
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NUM PINS NAME USB DMINUS 1 USB DPLUS 1 External USB USBRBIAS 1 Bias Resistor. USB PLL VDDUSBPLL Supply 1 Crystal Input 1 Crystal 1 Output NUM PINS NAME Ethernet TX 1 Data Out Negative Ethernet TX 1 Data Out ...
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... Refer to the device reference schematic for connection information. Note: EXRES AI Used for the internal bias circuits. Connect to an external resistor to ground. For LAN9500A/LAN9500Ai use 12.0K, 1%. For LAN9500/LAN9500i use 12.4K, 1%. VDDPLL P This pin must be connected to VDDCORE for proper operation. Refer to page 24 additional connection information. ...
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... TEST2 Note 3.3 This pin is a no-connect (NC) for LAN9500A/LAN9500Ai, but may be connected to VDD33A for backward compatibility with LAN9500/LAN9500i. Note 3.4 For LAN9500A/LAN9500Ai this pin provides additional PME related functionality. Refer to the respective pin descriptions and information. Revision 1.0 (05-17-10) PIN PIN NAME ...
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USB 2.0 to 10/100 Ethernet Controller Datasheet 3.2 Buffer Types BUFFER TYPE IS Schmitt-triggered Input IS_5V 5V Tolerant Schmitt-triggered Input O8 Output with 8mA sink and 8mA source OD8 Open-drain output with 8mA sink O12 Output with 12mA sink and ...
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Chapter 4 Power Connections Figure 4.1 illustrates the power connections for LAN950x. +3.3V 0.1 F VDD33IO 0.1 F VDD33IO 0.1 F VDD33IO 0.1 F VDD33IO 0.1 F VDD33IO 0.5A 120 @ 100MHz 0.1 F VDD33A 0.1 F VDD33A 0.1 F ...
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USB 2.0 to 10/100 Ethernet Controller Datasheet Chapter 5 EEPROM Controller (EPC) LAN950x may use an external EEPROM to store the default values for the USB descriptors and the MAC address. The EEPROM controller supports most “93C46” type EEPROMs. The ...
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... Bit -> GPIO(x+8) Pin Enabled for Wakeup Use. Note: 20h (LAN9500A/LAN9500Ai Only) GPIO PME Flags Note: EEPROM byte addresses past the indicated address can be used to store data for any purpose: LAN9500/LAN9500i - 1Dh LAN9500A/LAN9500Ai - 20h Revision 1.0 (05-17-10) Table 5.1 EEPROM Format (continued) Bits 7:3 Unused. 26 DATASHEET USB 2 ...
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USB 2.0 to 10/100 Ethernet Controller Datasheet Table 5.2 describes the Configuration Flags. BITS 7:6 RESERVED 5:4 (LAN9500A/LAN9500Ai Only, Otherwise RESERVED) PHY Boost This field provides the ability to boost the electrical drive strength of the HS output current to ...
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Table 5.3 describes the GPIO PME flags (LAN9500A/LAN9500Ai Only). BITS 7 GPIO PME Enable Setting this bit enables the assertion of the GPIO0 or GPIO8 pin result of a Wakeup (GPIO) pin, Magic Packet, or PHY Link Up. ...
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... Note: The Configuration Flags are affected by the PWR_SEL and RMT_WKP straps. SMSC LAN950x Family Table 5.3 GPIO PME Flags (continued) DESCRIPTION is 0, this bit is ignored. Table 5.4 EEPROM Defaults DEFAULT VALUE FFFFFFFFFFFFh 0424h DEVICE LAN9500/LAN9500i LAN9500A/LAN9500Ai 29 DATASHEET Table 5.4. 01h 04h 04h FAh ...
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... Note: The USB reset only loads the MAC address. 5.4 Examples of EEPROM Format Interpretation 5.4.1 LAN9500/LAN9500i Table 5.5 and Table 5.6 case of LAN9500/LAN9500i. Table 5.6 illustrates, byte by byte, how the EEPROM is formatted. Table 5.5 Dump of EEPROM Memory - LAN9500/LAN9500i OFFSET BYTE 0000h 0008h 0010h 0018h 0020h 0028h 0030h 0038h ...
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... USB 2.0 to 10/100 Ethernet Controller Datasheet Table 5.6 EEPROM Example - 256 Byte EEPROM - LAN9500/LAN9500i EEPROM EEPROM CONTENTS ADDRESS (HEX) 00h A5 01h - 06h 07h 01 08h 04 09h 04 0Ah - 0Bh 09 04 0Ch 0A 0Dh 0F 0Eh 10 0Fh 14 10h 10 11h 1C 12h 00 13h 00 14h 00 15h 00 16h 12 17h 24 18h ...
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... Table 5.6 EEPROM Example - 256 Byte EEPROM - LAN9500/LAN9500i (continued) EEPROM EEPROM CONTENTS ADDRESS (HEX) 20h-27h 28h 10 29h 03 2Ah-37h 38h 10 39h 03 3Ah-47h 48h 12 49h 01 4Ah-4Bh 00 02 4Ch FF 4Dh 00 4Eh 01 4Fh 40 50h-51h 24 04 52h-53h 00 95 54h-55h 00 01 56h 01 57h 02 58h 03 59h 01 5Ah 09 5Bh ...
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... USB 2.0 to 10/100 Ethernet Controller Datasheet Table 5.6 EEPROM Example - 256 Byte EEPROM - LAN9500/LAN9500i (continued) EEPROM EEPROM CONTENTS ADDRESS (HEX) 64h 04 65h 00 66h 00 67h 03 68h FF 69h 00 6Ah FF 6Bh 00 6Ch 12 6Dh 01 6Eh-6Fh 00 02 70h FF 71h 00 72h 01 73h 40 74h-75h 24 04 76h-77h 00 95 78h-79h ...
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... Table 5.6 EEPROM Example - 256 Byte EEPROM - LAN9500/LAN9500i (continued) EEPROM EEPROM CONTENTS ADDRESS (HEX) 88h 04 89h 00 8Ah 00 8Bh 03 8Ch FF 8Dh 00 8Eh FF 8Fh 00 90h- FFh - Revision 1.0 (05-17-10) DESCRIPTION Descriptor Type (Interface Descriptor - 04h) Number identifying this Interface Value used to select alternative setting ...
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USB 2.0 to 10/100 Ethernet Controller Datasheet 5.4.2 LAN9500A/LAN9500Ai Table 5.7 and Table 5.8 case of LAN9500A/LAN9500Ai. while Table 5.8 illustrates, byte by byte, how the EEPROM is formatted. Table 5.7 Dump of EEPROM Memory - LAN9500A/LAN9500Ai OFFSET BYTE 0000h ...
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Table 5.8 EEPROM Example - 256 Byte EEPROM - LAN9500A/LAN9500Ai EEPROM EEPROM CONTENTS ADDRESS (HEX) 00h A5 01h - 06h 07h 01 08h 04 09h 04 0Ah - 0Bh 09 04 0Ch 0A 0Dh ...
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USB 2.0 to 10/100 Ethernet Controller Datasheet Table 5.8 EEPROM Example - 256 Byte EEPROM - LAN9500A/LAN9500Ai (continued) EEPROM EEPROM CONTENTS ADDRESS (HEX) 20h 8A 21h 00 22h 0A 23h 03 24h - 2Bh ...
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Table 5.8 EEPROM Example - 256 Byte EEPROM - LAN9500A/LAN9500Ai (continued) EEPROM EEPROM CONTENTS ADDRESS (HEX) 65h 01 66h 00 67h A0 68h FA 69h 09 6Ah 04 6Bh 00 6Ch 00 6Dh 03 6Eh FF 6Fh 00 70h FF ...
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USB 2.0 to 10/100 Ethernet Controller Datasheet Table 5.8 EEPROM Example - 256 Byte EEPROM - LAN9500A/LAN9500Ai (continued) EEPROM EEPROM CONTENTS ADDRESS (HEX) 89h 01 8Ah 00 8Bh A0 8Ch FA 8Dh 09 8Eh 04 8Fh 00 90h 00 91h ...
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Chapter 6 PME Operation PME Operation is supported only by LAN9500A/LAN9500Ai. The device provides a mechanism for waking up a host system via PME mode of operation. PME signaling is only available while the device is operating in the self ...
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USB 2.0 to 10/100 Ethernet Controller Datasheet The Host Processor is connected to a Chipset containing the Host USB Controller (HC). The USB Host Controller interfaces to the device via the DP/DM USB signals. An Embedded Controller (EC) signals the ...
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Figure 6.2 flowcharts PME operation while in Internal PHY mode. The following conditions hold: EEPROM Configuration: GPIO PME Enable GPIO PME Configuration GPIO PME Length GPIO PME Polarity GPIO PME Buffer Type GPIO PME WOL Select GPIO10 Detection Select Power ...
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USB 2.0 to 10/100 Ethernet Controller Datasheet Host & Chipset Powered Off VBUS_DET Set Sets PME_MODE_SEL = 1 And Pulses PME_CLEAR Low Device Has EEPROM With GPIO PME Enable =1, Enters PME Mode Wakeup Event ...
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Chapter 7 NetDetach Operation NetDetach operation is supported only by LAN9500A/LAN9500Ai NetDetach is a mode of operation where the device detaches from the USB bus after the Ethernet cable is disconnected. This is advantageous for mobile devices attached ...
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USB 2.0 to 10/100 Ethernet Controller Datasheet Ethernet SMSC LAN9500A/ LAN9500Ai SMSC LAN950x Family 1 Insert Ethernet Cable 2 USB Electricals Attach LAN9500A enumerates and 3 the driver is loaded Figure 7.2 Device Attach 45 DATASHEET Revision 1.0 (05-17-10) ...
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... Note 8 +70 Note 8.5 +/-8kV for LAN9500/LAN9500i, +/-5kV for LAN9500A/LAN9500Ai Note 8.6 Performed by independent 3rd party test facility. *Stresses exceeding those listed in this section could cause permanent damage to the device. This is a stress rating only. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. Functional operation of the device at any condition exceeding those indicated in Section 8.2, " ...
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... Note: All current consumption and power dissipation values were measured at VDD33IO and VDD33A equal to 3.3V. 8.3.1 SUSPEND0 Table 8.1 Power Consumption/Dissipation - SUSPEND0 (LAN9500/LAN9500i) PARAMETER Supply current (VDD33IO, VDD33A) (Device Only) Power Dissipation (Device Only) Power Dissipation (Device and Ethernet components) Table 8 ...
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... Supply current (VDD33IO, VDD33A) (Device Only) Power Dissipation (Device Only) Power Dissipation (Device and Ethernet components) 8.3.3 SUSPEND2 Table 8.5 Power Consumption/Dissipation - SUSPEND2 (LAN9500/LAN9500i) PARAMETER Supply current (VDD33IO, VDD33A) (Device Only) Power Dissipation (Device Only) Power Dissipation (Device and Ethernet components) Table 8 ...
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... Supply current (VDD33IO, VDD33A) (Device Only) Power Dissipation (Device Only) Power Dissipation (Device and Ethernet components) 8.3.5 Operational Table 8.8 Operational Power Consumption/Dissipation (LAN9500/LAN9500i) PARAMETER 100BASE-TX Full Duplex (USB High-Speed) Supply current (VDD33IO, VDD33A) (Device Only) Power Dissipation (Device Only) Power Dissipation (Device and Ethernet components) ...
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... Power Dissipation (Device Only) Power Dissipation (Device and Ethernet components) 8.3.6 Customer Evaluation Board Operational Current Consumption*** Table 8.10 CEB Operational Current Consumption (LAN9500/LAN9500i) PARAMETER 100BASE-TX Full Duplex (USB High-Speed) Total SMSC Customer Evaluation Board Current Consumption Table 8.11 CEB Operational Current Consumption (LAN9500A/LAN9500Ai) ...
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USB 2.0 to 10/100 Ethernet Controller Datasheet 8.4 DC Specifications PARAMETER SYMBOL IS Type Input Buffer Low Input Level V High Input Level V Negative-Going Threshold V Positive-Going Threshold V IHT SchmittTrigger Hysteresis V HYS ( IHT ...
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Note 8.8 This is the total 5.5V input leakage for the entire device. Note 8.9 XI can optionally be driven from a 25MHz single-ended clock oscillator. Table 8.13 100BASE-TX Transceiver Characteristics PARAMETER Peak Differential Output Voltage High Peak Differential Output ...
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USB 2.0 to 10/100 Ethernet Controller Datasheet 8.5 AC Specifications This section details the various AC timing specifications of the device. Note: The MII timing adheres to the IEEE 802.3 specification. Refer to the IEEE 802.3 specification for additional MII ...
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Power-On Configuration Strap Valid Timing Figure 8.2 illustrates the configuration strap valid timing requirement in relation to power-on. In order for valid configuration strap values to be read at power-on, the following timing requirements must be met. VDD33IO Configuration ...
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USB 2.0 to 10/100 Ethernet Controller Datasheet 8.5.3 Reset and Configuration Strap Timing Figure 8.3 illustrates the nRESET pin timing requirements and its relation to the configuration strap pins and output drive. Assertion of nRESET is not a requirement. However, ...
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EEPROM Timing The following specifies the EEPROM timing requirements for the device: EECS t EECLK EEDO EEDI EEDI (VERIFY) SYMBOL DESCRIPTION t EECLK Cycle time ckcyc t EECLK High time ckh t EECLK Low time ckl t EECS high ...
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USB 2.0 to 10/100 Ethernet Controller Datasheet 8.5.5 MII Interface Timing This section specifies the MII interface transmit and receive timing. TXCLK TXD[3:0] TXEN SYMBOL DESCRIPTION t TXCLK period clkp t TXCLK high time clkh t TXCLK low time clkl ...
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RXCLK RXD[3:0] t hold RXDV SYMBOL DESCRIPTION t RXCLK period clkp t RXCLK high time clkh t RXCLK low time clkl t RXD[3:0], RXDV setup time to rising edge of su RXCLK t RXD[3:0], RXDV hold time after rising edge ...
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USB 2.0 to 10/100 Ethernet Controller Datasheet 8.5.6 Turbo MII Interface Timing This section specifies the Turbo MII interface transmit and receive timing. TXCLK TXD[3:0] TXEN Table 8.20 Turbo MII Transmit Timing Values SYMBOL DESCRIPTION t TXCLK period clkp t ...
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RXCLK RXD[3:0] t hold RXDV Table 8.21 Turbo MII Receive Timing Values SYMBOL DESCRIPTION t RXCLK period clkp t RXCLK high time clkh t RXCLK low time clkl t RXD[3:0], RXDV setup time to rising edge of su RXCLK t ...
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USB 2.0 to 10/100 Ethernet Controller Datasheet 8.6 Clock Circuit The device can accept either a 25MHz crystal (preferred 25MHz single-ended clock oscillator (+/- 50ppm) input. If the single-ended clock oscillator method is implemented, XO should be left ...
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Chapter 9 Package Outline MIN NOMINAL A 0.70 0.85 A1 0.00 0. D/E 7.85 8.00 D1/E1 7.55 7.75 D2/E2 5.80 5.90 L 0.30 0.40 b 0.18 0. 0.50 BSC Revision 1.0 (05-17-10) Figure ...
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USB 2.0 to 10/100 Ethernet Controller Datasheet Notes: 1. All dimensions are in millimeters unless otherwise noted. 2. Position tolerance of each terminal and exposed pad is +/- 0. maximum material condition. Dimension “b” applies to plated terminals ...
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Chapter 10 Datasheet Revision History REVISION LEVEL AND DATE SECTION/FIGURE/ENTRY Rev. 1.0 Initial Release (05-17-10) Revision 1.0 (05-17-10) Table 10.1 Customer Revision History 64 DATASHEET USB 2.0 to 10/100 Ethernet Controller Datasheet CORRECTION SMSC LAN950x Family ...