DS90CR216AMTDX National Semiconductor, DS90CR216AMTDX Datasheet - Page 3

• Manufacturer Part Number: DS90CR216AMTDX
• Manufacturer: National Semiconductor

Specifications of DS90CR216AMTDX

• Number Of Elements: 3
• Input Type: CMOS/TTL
• Operating Supply Voltage (typ): 3.3V
• Differential Input High Threshold Voltage: 100mV
• Diff. Input Low Threshold Volt: -100mV
• Operating Temp Range: -40C to 85C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 48
• Package Type: TSSOP
• Number Of Receivers: 3
• Number Of Drivers: 21
• Lead Free Status / RoHS Status: Not Compliant

ICCRZ
CLHT
CHLT
RSPos0
RSPos1
RSPos2
RSPos3
RSPos4
RSPos5
RSPos6
RSPos0
RSPos1
RSPos2
RSPos3
RSPos4
RSPos5
RSPos6
RSKM
RCOP
RCOH
RCOL
RSRC
RHRC
RCOH
RCOL
RSRC
RHRC
RCCD
RPLLS
RPDD
Symbol
Symbol
Note 1: “Absolute Maximum Ratings” are those values beyond which the safety of the device cannot be guaranteed. They are not meant to imply that the device
should be operated at these limits. The tables of “Electrical Characteristics” specify conditions for device operation.
Note 2: Typical values are given for V
Note 3: Current into device pins is defined as positive. Current out of device pins is defined as negative. Voltages are referenced to ground unless otherwise
specified (except V
Receiver Switching Characteristics
Over recommended operating supply and temperature ranges unless otherwise specified
Note 4: Receiver Skew Margin is defined as the valid data sampling region at the receiver inputs. This margin takes into account the transmitter pulse positions
(min and max) and the receiver input setup and hold time (internal data sampling window - RSPos). This margin allows for LVDS interconnect skew, inter-symbol
interference (both dependent on type/length of cable), and clock jitter (less than 250 ps).
Note 5: Total latency for the channel link chipset is a function of clock period and gate delays through the transmitter (TCCD) and receiver (RCCD). The total
latency for the 215/285 transmitter and 216A/286A receiver is: (T + TCCD) + (2*T + RCCD), where T = Clock period.
Receiver Supply Current
Power Down
CMOS/TTL Low-to-High Transition Time
CMOS/TTL High-to-Low Transition Time
Receiver Input Strobe Position for Bit 0
10)
Receiver Input Strobe Position for Bit 1
Receiver Input Strobe Position for Bit 2
Receiver Input Strobe Position for Bit 3
Receiver Input Strobe Position for Bit 4
Receiver Input Strobe Position for Bit 5
Receiver Input Strobe Position for Bit 6
Receiver Input Strobe Position for Bit 0
(Figure
Receiver Input Strobe Position for Bit 1
Receiver Input Strobe Position for Bit 2
Receiver Input Strobe Position for Bit 3
Receiver Input Strobe Position for Bit 4
Receiver Input Strobe Position for Bit 5
Receiver Input Strobe Position for Bit 6
RxIN Skew Margin
RxCLK OUT Period
RxCLK OUT High Time
RxCLK OUT Low Time
RxOUT Setup to RxCLK OUT
RxOUT Hold to RxCLK OUT
RxCLK OUT High Time
RxCLK OUT Low Time
RxOUT Setup to RxCLK OUT
RxOUT Hold to RxCLK OUT
RxCLK IN to RxCLK OUT Delay @ 25°C, V
Receiver Phase Lock Loop Set
Receiver Power Down Delay
OD
and ΔV
9,
Figure
Parameter
OD
).
10)
(Note
CC
(Figure
= 3.3V and T
(Figure
(Figure
(Figure 3
(Figure 3
4)
3)
(Figure 11
(Figure 3
(Figure 3
(Figure 8
(Figure 3
(Figure 3
Parameter
3)
3)
(Figure 5
A
)
)
= +25C.
)
)
(Figure
)
)
)
)
Power Down = Low
Receiver Outputs Stay Low during
Power Down Mode
)
(Figure 2
(Figure 2
CC
= 3.3V
9,
Figure
)
)
3
(Note 5)(Figure 4
f = 40 MHz
f = 66 MHz
f = 40 MHz
f = 66 MHz
f = 40 MHz
f = 66 MHz
Conditions
)
11.6
15.1
18.8
22.5
11.7
13.9
10.0
10.0
Min
490
400
1.0
4.5
8.1
0.7
2.9
5.1
7.3
9.5
6.5
6.0
5.0
5.0
4.5
4.0
3.5
15
Min
11.9
15.6
19.2
22.9
12.1
14.3
12.2
11.0
11.6
11.6
Typ
1.8
1.4
5.0
8.5
1.1
3.3
5.5
7.7
9.9
7.6
6.3
7.3
6.3
5.0
2
T
Typ
10
Max
2.15
9.15
12.6
16.3
19.9
23.6
10.2
12.4
14.6
5.8
1.4
3.6
5.8
8.0
7.5
50
10
5
5
1
Max
55
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Units
Units
ms
μA
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ps
ps
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
μs