DS90CR216AMTDX National Semiconductor, DS90CR216AMTDX Datasheet - Page 10

• Manufacturer Part Number: DS90CR216AMTDX
• Manufacturer: National Semiconductor

Specifications of DS90CR216AMTDX

• Number Of Elements: 3
• Input Type: CMOS/TTL
• Operating Supply Voltage (typ): 3.3V
• Differential Input High Threshold Voltage: 100mV
• Diff. Input Low Threshold Volt: -100mV
• Operating Temp Range: -40C to 85C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 48
• Package Type: TSSOP
• Number Of Receivers: 3
• Number Of Drivers: 21
• Lead Free Status / RoHS Status: Not Compliant

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RxIN+
RxIN−
RxOUT
RxCLK IN+
RxCLK IN−
RxCLK OUT
PWR DOWN
V
GND
PLL V
PLL GND
LVDS V
LVDS GND
RxIN+
RxIN−
RxOUT
RxCLK IN+
RxCLK IN−
RxCLK OUT
PWR DOWN
V
GND
PLL V
PLL GND
LVDS V
LVDS GND
CC
CC
DS90CR286A Pin Descriptions —
MTD56 Package — 28-Bit Channel
Link Receiver
DS90CR216A Pin Descriptions —
MTD48 Package — 21-Bit Channel
Link Receiver
Note 8: These receivers have input failsafe bias circuitry to guarantee a stable receiver output for floating or terminated receiver inputs. Under these conditions
receiver inputs will be in a HIGH state. If a clock signal is present, outputs will all be HIGH; if the clock input is also floating/terminated outputs will remain in the
last valid state. A floating/terminated clock input will result in a LOW clock output.
Pin Name
Pin Name
CC
CC
CC
CC
I/O No
I/O No
O
O
O
O
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
28 TTL level data outputs.
21 TTL level data outputs.
4
4
1
1
1
1
4
5
1
2
1
3
3
3
1
1
1
1
4
5
1
2
1
3
.
.
Positive LVDS differentiaI data inputs.
Negative LVDS differential data inputs.
Positive LVDS differential clock input.
Negative LVDS differential clock input.
TTL Ievel clock output. The rising edge acts as data strobe.
TTL level input. When asserted (low input) the receiver outputs are low.
Power supply pins for TTL outputs.
Ground pins for TTL outputs.
Power supply for PLL.
Ground pin for PLL.
Power supply pin for LVDS inputs.
Ground pins for LVDS inputs.
Positive LVDS differentiaI data inputs.
Negative LVDS differential data inputs.
Positive LVDS differential clock input.
Negative LVDS differential clock input.
TTL Ievel clock output. The rising edge acts as data strobe.
TTL level input. When asserted (low input) the receiver outputs are low.
Power supply pins for TTL outputs.
Ground pins for TTL outputs.
Power supply for PLL.
Ground pin for PLL.
Power supply pin for LVDS inputs.
Ground pins for LVDS inputs.
10
(Note
(Note
8)
Description
Description
8)