SPT9101SCU Fairchild Semiconductor, SPT9101SCU Datasheet

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SPT9101SCU

Manufacturer Part Number
SPT9101SCU
Description
Manufacturer
Fairchild Semiconductor
Datasheet

Specifications of SPT9101SCU

Number Of Sample And Hold Elements
1
Power Supply Requirement
Dual
Single Supply Voltage (typ)
Not RequiredV
Single Supply Voltage (min)
Not RequiredV
Single Supply Voltage (max)
Not RequiredV
Lead Free Status / RoHS Status
Compliant
FEATURES
• Second Source of AD9101
• 350 MHz Sampling Bandwidth
• 125 MHz Sampling Rate
• Excellent Hold Mode Distortion
• 7 ns Acquisition Time to 0.1%
• <1 ps Aperture Jitter
• 66 dB Feedthrough Rejection at 50 MHz
• Low Spectral Noise Density
GENERAL DESCRIPTION
The SPT9101 is a high-speed track-and-hold amplifier de-
signed for a wide range of use. The SPT9101 is capable of
sampling at speeds up to 125 MSPS with resolutions ranging
from 8 to 12 bits. Trim programmable internal hold and
compensation capacitors provide for optimized input band-
width and slew rate versus noise performance.
BLOCK DIAGRAM
-75 dB at 50 MSPS (23 MHz V
-62 dB at 100 MSPS (48 MHz V
V In
CLK NCLK
IN
Sampler
+
-
IN
)
)
C H
OLD
125 MSPS SAMPLE-AND-HOLD AMPLIFIER
R
RTN
APPLICATIONS
• Test Instrumentation Equipment
• RF Demodulation Systems
• High Performance CCD Capture
• Digital Sampling Oscilloscopes
• Commercial and Military Radar
• High-Speed DAC Deglitching
The performance of this device makes it an excellent front
end driver for a wide range of ADCs on the market today.
Significant improvements in dynamic performance can be
achieved by using this device ahead of virtually all ADCs that
do not have an internal track-and-hold.
The SPT9101 is offered in 20-lead SOIC and LCC packages
over the industrial temperature range and in die form. Contact
the factory for military and /833 package options.
+
-
Amp
4X
3R
SPT9101
V O
UT

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SPT9101SCU Summary of contents

Page 1

FEATURES • Second Source of AD9101 • 350 MHz Sampling Bandwidth • 125 MHz Sampling Rate • Excellent Hold Mode Distortion - MSPS (23 MHz V - 100 MSPS (48 MHz V • ...

Page 2

ABSOLUTE MAXIMUM RATING (Beyond which damage may occur) Supply Voltages Supply Voltage (+V ) ................................ -0 Supply Voltage (-V ) ................................. - +0 Input Voltages Analog Input Voltage ................................................ 5 V ...

Page 3

ELECTRICAL SPECIFICATIONS +V =+5 =-5 =100 , unless otherwise specified LOAD PARAMETERS Hold Mode Dynamics Worst Harmonic p-p Out Worst Harmonic p-p Out Worst Harmonic V ...

Page 4

TEST LEVEL CODES All electrical characteristics are subject to the following conditions: All parameters having min/ max specifications are guaranteed. The Test Level column indicates the specific device test- ing actually performed during production and Quality Assurance inspection. Any blank ...

Page 5

Figure 2 - Typical Interface Circuit + 2.2 µF -A5 IN+ CLK SPT, HCMP96850 4 GND V t IN- LE 1,16 6 THEORY OF OPERATION The ...

Page 6

The RTN pin may be tied to an external voltage to generate an offset at the output. V must be kept to less than 2.7 V Out typical output swing with an external reference voltage Out at the ...

Page 7

A Bottom View PACKAGE OUTLINES 20-Lead LCC H SYMBOL Pin 20-Lead SOIC SYMBOL ...

Page 8

... RTN 1 2 RTN N SOIC 6 GND GND CLK LCC GND 16 (Bottom View N/C 14 ORDERING INFORMATION PART NUMBER SPT9101SIS SPT9101SIC SPT9101SCU *Please see die specification for guranteed electrical performance. PIN FUNCTIONS Name 20 V Out RTN + N/C GND CLK NCLK - GND N N/C V OUT NCLK ...

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