spt9101 Fairchild Semiconductor, spt9101 Datasheet

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spt9101

Manufacturer Part Number
spt9101
Description
125 Msps Sample-and-hold Amplifier
Manufacturer
Fairchild Semiconductor
Datasheet

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FEATURES
• Second Source of AD9101
• 350 MHz Sampling Bandwidth
• 125 MHz Sampling Rate
• Excellent Hold Mode Distortion
• 7 ns Acquisition Time to 0.1%
• <1 ps Aperture Jitter
• 66 dB Feedthrough Rejection at 50 MHz
• Low Spectral Noise Density
GENERAL DESCRIPTION
The SPT9101 is a high-speed track-and-hold amplifier de-
signed for a wide range of use. The SPT9101 is capable of
sampling at speeds up to 125 MSPS with resolutions ranging
from 8 to 12 bits. Trim programmable internal hold and
compensation capacitors provide for optimized input band-
width and slew rate versus noise performance.
BLOCK DIAGRAM
-75 dB at 50 MSPS (23 MHz V
-62 dB at 100 MSPS (48 MHz V
V In
CLK NCLK
IN
Sampler
+
-
IN
)
)
C H
OLD
125 MSPS SAMPLE-AND-HOLD AMPLIFIER
R
RTN
APPLICATIONS
• Test Instrumentation Equipment
• RF Demodulation Systems
• High Performance CCD Capture
• Digital Sampling Oscilloscopes
• Commercial and Military Radar
• High-Speed DAC Deglitching
The performance of this device makes it an excellent front
end driver for a wide range of ADCs on the market today.
Significant improvements in dynamic performance can be
achieved by using this device ahead of virtually all ADCs that
do not have an internal track-and-hold.
The SPT9101 is offered in 20-lead SOIC and LCC packages
over the industrial temperature range and in die form. Contact
the factory for military and /833 package options.
+
-
Amp
4X
3R
SPT9101
V O
UT

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spt9101 Summary of contents

Page 1

... Low Spectral Noise Density GENERAL DESCRIPTION The SPT9101 is a high-speed track-and-hold amplifier de- signed for a wide range of use. The SPT9101 is capable of sampling at speeds up to 125 MSPS with resolutions ranging from bits. Trim programmable internal hold and compensation capacitors provide for optimized input band- width and slew rate versus noise performance ...

Page 2

... VI IV Full Temp 0. 200 MHz V 10 MHz SPT9101 MIN TYP MAX 3.93 4.0 4.07 3 2.4 2 100 450 3 30 -1.8 -1.5 -1.0 -0.8 150 180 1100 1400 55 270 3.9 UNITS V/V V mV/V mV MHz SPT9101 12/30/99 ...

Page 3

... V < 551 VI 449 ) is 20 ns, the accumulated H MAX UNITS MHz mV/s mV rms pV 663 mW 561 mW SPT9101 12/30/99 ...

Page 4

... Hold NCLK TIMING SPECIFICATION DEFINITIONS ACQUISITION TIME This is the time it takes the SPT9101 to acquire the analog signal at the internal hold capacitor when it makes a transition from hold mode to track mode. (See figure 1.) The acquisition time is measured from the 50% input clock transition point to the point when the signal is within a specified error band at the internal hold capacitor (ahead of the output amplifier) ...

Page 5

... TYPICAL INTERFACE CIRCUIT BOOTSTRAP CAPACITOR The SPT9101 does not require the bootstrap capacitor that is required on the AD9101 between pins 3 and 19. Because pins 3 and 19 are No Connects on the SPT9101, it will work well in existing AD9101 sockets ...

Page 6

... Input Frequency (MHz) SAMPLER FOR 12-BIT ADC APPLICATION The SPT9101 was specifically designed for applications where improved bandwidth performance is required. Figure 3 shows as simple block diagram of the SPT9101 as a sampler ahead of the SPT7922 12-bit, 30 MSPS ADC. | 2.7 V Out Figure 3 - Sampler for 12-Bit ADC ...

Page 7

... INCHES MILLIMETERS MIN MAX MIN 0.291 0.299 7.40 0.394 0.419 10.00 0.496 0.512 12.60 0.050 typ 1.27 typ 0.014 0.019 0.35 0.004 0.012 0.10 0.093 0.104 2.35 0.009 0.013 0.23 0.016 . 0.050 0.40 I MAX 1.02 1.27 1.40 9.14 1.68 0.51 0.71 1.91 MAX 7.60 10.65 13.00 0.49 0.30 2.65 0.32 1.27 SPT9101 12/30/99 ...

Page 8

... I/O Function I Gain Set Resistor Return Power Supply I Ground I True ECL T/H Clock I Complement ECL T/H Clock I -5.2 V Power Supply - No Connection I Analog Signal Input O Analog Signal Output TEMPERATURE RANGE -40 to +85 C -40 to +85 C +25 C © Copyright 2002 Fairchild Semiconductor Corporation SPT9101 12/30/99 ...

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