AD73411BBZ-80 Analog Devices Inc, AD73411BBZ-80 Datasheet - Page 20

• Manufacturer Part Number: AD73411BBZ-80
• Manufacturer: Analog Devices Inc

Specifications of AD73411BBZ-80

• Single Supply Voltage (typ): 3.3V
• Single Supply Voltage (min): 3V
• Single Supply Voltage (max): 3.6V
• Package Type: BGA
• Lead Free Status / RoHS Status: Compliant

AD73411
AFE Interfacing
The AFE section SPORT (SPORT2) can be interfaced to either
SPORT0 or SPORT1 of the DSP section. Both serial input and
output data use an accompanying frame synchronization signal
which is active high one clock cycle before the start of the 16-bit
word or during the last bit of the previous word if transmission
is continuous. The serial clock (SCLK) is an output from the
codec and is used to define the serial transfer rate to the DSP’s
Tx and Rx ports. Two primary configurations can be used: the
first is shown in Figure 10 where the DSP’s Tx data, Tx Frame
Sync, Rx data and Rx Frame Sync are connected to the codec’s
SDI, SDIFS, SDO and SDOFS respectively. This configuration,
referred to as indirectly coupled or nonframe sync loop-back,
has the effect of decoupling the transmission of input data from
the receipt of output data. The delay between receipt of codec
output data and transmission of input data for the codec is
determined by the DSP’s software latency. When programming
the DSP serial port for this configuration, it is necessary to set
the Rx Frame Sync as an input and the Tx Frame Sync as an
output generated by the DSP. This configuration is most useful
when operating in mixed mode, as the DSP has the ability to
decide how many words (either DAC or control) can be sent to
the codecs. This means that full control can be implemented
over the device configuration as well as updating the DAC in a
given sample interval. The second configuration (shown in
Figure 11) has the DSP’s Tx data and Rx data connected to the
codec’s SDI and SDO, respectively while the DSP’s Tx and Rx
frame syncs are connected to the codec’s SDIFS and SDOFS.
In this configuration, referred to as directly coupled or frame
sync loop-back, the frame sync signals are connected together
and the input data to the codec is forced to be synchronous with
the output data from the codec. The DSP must be programmed
so that both the Tx Frame Sync and Rx Frame Sync are inputs
as the codec SDOFS will be input to both. This configuration
guarantees that input and output events occur simultaneously
and is the simplest configuration for operation in normal Data
Mode. Note that when programming the DSP in this configuration
it is advisable to preload the Tx register with the first control
word to be sent before the codec is taken out of reset. This
ensures that this word will be transmitted to coincide with the
first output word from the device(s).
REFOUT
REFCAP
VOUTN
VOUTP
VINP
VINN
LOOP-BACK
+6/–15dB
ANALOG
SELECT
PGA
REFERENCE
CONTINUOUS
LOW-PASS
FILTER
TIME
INVERT
SINGLE-ENDED
V
AD73411
REF
ENABLE
0/38dB
PGA
Cascade Operation
The AD73411 has been designed to support up to eight codecs in
a cascade connected to a single serial port. The SPORT interface
protocol has been designed so that device addressing is built
into the packet of information sent to the device. This allows the
cascade to be formed with no extra hardware overhead for
control signals or addressing. A cascade can be formed in
either of the two modes previously discussed.
There may be some restrictions in cascade operation due to the
number of devices configured in the cascade and the serial clock
rate chosen. Table XV details the requirements for SCLK rate
for cascade lengths from 1 to 8 devices. This assumes a directly
coupled frame sync arrangement as shown in Figure 11.
SCLK
DMCLK
DMCLK/2
DMCLK/4
DMCLK/8
When using the indirectly coupled frame sync configuration in
cascaded operation it is necessary to be aware of the restrictions
in sending data to all devices in the cascade. Effectively, the
time allowed is given by the sampling interval (256/DMCLK)
which is 15.625 µs for a sample rate of 64 kHz. In this interval, the
DSP must transfer N × 16 bits of information where N is the
number of devices in the cascade. Each bit will take 1/SCLK
and, allowing for any latency between the receipt of the Rx
interrupt and the transmission of the Tx data, the relationship
for successful operation is given by:
The interrupt latency will include the time between the ADC
sampling event and the Rx interrupt being generated in the
DSP—this should be 16 SCLK cycles.
256/DMCLK > ((N × 16/SCLK) + T
SECTION
SECTION
DSP
DSP
Table XV. Cascade Options
1




TFS
DT
SCLK
RFS
TFS
DT
SCLK
RFS
DR
DR
Number of Devices in Cascade
2




3



X
4



X
SDOFS
SDOFS
SDIFS
SDIFS
SCLK
SCLK
SDO
SDO
SDI
SDI
INTERRUPT LATENCY
5


X
X
SECTION
SECTION
6


X
X
AFE
AFE
7


X
X
)
8


X
X