AD73411BBZ-80 Analog Devices Inc, AD73411BBZ-80 Datasheet - Page 12

• Manufacturer Part Number: AD73411BBZ-80
• Manufacturer: Analog Devices Inc

Specifications of AD73411BBZ-80

• Single Supply Voltage (typ): 3.3V
• Single Supply Voltage (min): 3V
• Single Supply Voltage (max): 3.6V
• Package Type: BGA
• Lead Free Status / RoHS Status: Compliant

AD73411
ADC Coding
The ADC coding scheme is in twos complement format (see
Figure 5). The output words are formed by the decimation
filter, which grows the word length from the single-bit output of
the sigma-delta modulator to a 15-bit word, which is the 16-bit
transfer being used as a flag bit to indicate either control or data
in the frame.
Decoder Channel
The decoder channel consists of a digital interpolator, digital
sigma-delta modulator, a single bit digital-to-analog converter
(DAC), an analog smoothing filter and a programmable gain
amplifier with differential output.
DAC Coding
The DAC coding scheme is in twos complement format with
0x7FFF being full-scale positive and 0x8000 being full-scale
negative.
Interpolation Filter
The anti-imaging interpolation filter is a sinc-cubed digital filter
which upsamples the 16-bit input words from the SPORT
input rate of DMCLK/M (where M depends on the sample rate
setting (M = 256 @ 64 kHz; M = 512 @ 32 kHz, M = 1024 @
16 kHz, M = 2048 @ 8 kHz), to a rate of DMCLK/8 while
filtering to attenuate images produced by the interpolation pro-
cess. Its Z transform is given as: [(1–Z
determined by the sampling rate (N = 32 @ 64 kHz, N = 64 @
32 kHz, N = 128 @ 16 kHz, N = 256 @ 8 kHz). The DAC
receives 16-bit samples from the host DSP processor at a rate of
DMCLK/M. If the host processor fails to write a new value to
the serial port, the existing (previous) data is read again. The
data stream is filtered by the anti-imaging interpolation filter,
but there is an option to bypass the interpolator for the mini-
mum group delay configuration by setting the IBYP bit (CRE:5) of
Control Register E. The interpolation filter has the same charac-
teristics as the ADC’s antialiasing decimation filter.
ANALOG
ANALOG
INPUT
INPUT
V
V
V
REF
REF
V
REF
REF
+ (V
– (V
– (V
+ (V
REF
REF
REF
REF
0.32875)
0.32875)
0.6575)
0.6575)
V
V
REF
REF
10...00
10...00
ADC CODE SINGLE-ENDED
ADC CODE DIFFERENTIAL
V
V
V
INN
V
INN
–N
INP
INP
00...00
00...00
)/(1–Z
–1
)]
3
01...11
01...11
where N is
The output of the interpolation filter is fed to the DAC’s digital
sigma-delta modulator, which converts the 16-bit data to 1-bit
samples at a rate of DMCLK/8. The modulator noise-shapes
the signal so that errors inherent to the process are minimized
in the passband of the converter. The bitstream output of the
sigma-delta modulator is fed to the single bit DAC where it is
converted to an analog voltage.
Analog Smoothing Filter and PGA
The output of the single-bit DAC is sampled at DMCLK/8,
therefore it is necessary to filter the output to reconstruct the
low frequency signal. The decoder’s analog smoothing filter
consists of a continuous-time filter preceded by a third-order
switched-capacitor filter. The continuous-time filter forms part
of the output programmable gain amplifier (PGA). The PGA
can be used to adjust the output signal level from –15 dB to
+6 dB in 3 dB steps, as shown in Table II. The PGA gain is
set by bits OGS0, OGS1 and OGS2 (CRD:4-6) in Control
Register D.
OGS2
0
0
0
0
1
1
1
1
Differential Output Amplifiers
The decoder has a differential analog output pair (VOUTP and
VOUTN). The output channel can be muted by setting the
MUTE bit (CRD:7) in Control Register D. The output signal is
dc-biased to the codec’s on-chip voltage reference.
Voltage Reference
The AD73411 reference, REFCAP, is a bandgap reference
that provides a low noise, temperature-compensated reference
to the DAC and ADC. A buffered version of the reference is
also made available on the REFOUT pin and can be used to
bias other external analog circuitry. The reference has a default
nominal value of 1.2 V.
The reference output (REFOUT) can be enabled for biasing
external circuitry by setting the RU bit (CRC:6) of CRC.
AFE Serial Port (SPORT2)
The AFE section communicates with the DSP section via its
bidirectional synchronous serial port (SPORT2), which interfaces
to either SPORT0 or SPORT1 of the DSP section. SPORT2 is
used to transmit and receive digital data and control information.
This allows other single or dual codec devices to be cascaded
together (up to a limit of eight codec units).
In both transmit and receive modes, data is transferred at the
serial clock (SCLK2) rate with the MSB being transferred first.
Communications between the AFE section and the DSP section
must always be initiated by the AFE section (AFE is in master
mode—DSP SPORT is in slave mode). This ensures that there
is no collision between input data and output samples.
Table II. PGA Settings for the Decoder Channel
OGS1
0
0
1
1
0
0
1
1
OGS0
0
1
0
1
0
1
0
1
Gain (dB)
6
3
0
–3
–6
–9
–12
–15