SGTL5000XNAA3R2 Freescale, SGTL5000XNAA3R2 Datasheet - Page 14

• Manufacturer Part Number: SGTL5000XNAA3R2
• Manufacturer: Freescale

Specifications of SGTL5000XNAA3R2

• Single Supply Voltage (typ): 1.8/2.5/3.3V
• Lead Free Status / RoHS Status: Compliant

used. Each output from the source select switch has its own
register field that is used to select what input is routed to that
output.
and then out to the DAC (headphone) outputs write
SSS_CTRL->DAP_SELECT to 0x1 (selects I2S_IN) and
SSS_CTRL->DAC_SELECT to 0x3 (selects DAP output).
ANALOG INPUT BLOCK
microphone input with mic bias (in the 32 QFN package).
Either input can be routed to the ADC. The line input can also
configured to bypass the CODEC and be routed the analog
input directly to the headphone output.
Line Inputs
sources such as an FM radio or MP3 input.
inputs through series coupling capacitors. The suggested
value is shown in the typical application diagram in
Applications.
ADC.
by writing CHIP_ANA_CTRL->SELECT_HP. This selection
bypasses the ADC and audio switch and routes the line input
directly to the headphone output to enable a very low power
pass through.
Microphone Input
voice recording.
is can be programmed with the CHIP_MIC_CTRL-
>BIAS_VOLT register field. Values from 1.25 V to 3.00 V are
supported in 0.25 V steps. Mic bias should be set less than
200 mV from VDDA, e.g. with VDDA at 1.70 V, Mic bias
should be set no greater than 1.50 V.
coupling capacitor. The suggested value is shown in the
typical connection diagram.
CHIP_MIC_CTRL->GAIN register field. Values of 0 dB,
+20 dB, +30 dB and +40 dB are available.
ADC
either the line input or a microphone. The register field
CHIP_ANA_CTRL->SELECT_ADC controls this selection.
The output of the ADC feeds the audio switch.
+22.5 dB of gain in 1.5 dB steps. A bit is available that shifts
this range down by 6.0 dB to effectively provide -6.0 dB to
14
SGTL500
FUNCTIONAL DESCRIPTION
FUNCTIONAL INTERNAL BLOCK DESCRIPTION
To configure a route, the CHIP_SSS_CTRL register is
For example, to route the I
The analog input block contains a stereo line input and a
One stereo line input is provided for connection to line
The source should be connected to the left and right line
As detailed in ADC, the line input can be routed to the
The line input can also be routed to the headphone output
One mono microphone input is provided for uses such as
Mic bias is provided in the 32QFN package. The mic bias
The microphone should be connected through a series
The microphone has programmable gain through the
The SGTL5000 contains an ADC who takes its input from
The ADC has its own analog gain stage that provides 0 to
2
S digital input through the DAP
Typical
+16.5 dB of gain. The ADC gain is controlled in the
CHIP_ANA_ADC_CTRL register.
prevent any volume change until a zero-volt crossing of the
audio signal is detected. This helps in eliminating pop or other
audio anomalies. If the ADC is to be used, the chip reference
bias current should not be set to -50% when in 3.0 V mode.
ANALOG OUTPUTS
used to drive a headphone output and a line output. The DAC
receives its input from the audio switch. The headphone
output and the line output can be driven at the same time
from the DAC.
line input bypassing the ADC and DAC for a very low power
mode of operation.
output is powered by VDDIO. This allows the headphone
output to be run at the lowest possible voltage while the line
output can still meet line output level requirements.
DAC
dedicated line output.
to 0 dB in ~0.5 dB step sizes. This volume is shared among
headphone output and line output. The register
CHIP_DAC_VOL controls the DAC volume.
Headphone
used to drive a headphone load or a line level output. The
headphone output has its own independent analog volume
control with a volume range of -52 dB to +12 dB in 0.5 dB
step sizes. This volume control can be used in addition to the
DAC volume control. For best performance the DAC volume
control should be left at 0 dB until the headphone is brought
to its lowest setting of -52 dB. The register
CHIP_ANA_HP_CTRL is used to control the headphone
volume.
controlled by the register field CHIP_ANA_CTRL-
>MUTE_HP.
CHIP_ANA_CTRL->SELECT_HP. This selection bypasses
the ADC and audio switch and routes the line input directly to
the headphone output to enable a very low power pass
through. When the line input is routed to the headphone
output, only the headphone analog volume and mute will
affect the headphone output.
which, as previously described, will prevent any volume
change until a zero-volt crossing of the audio signal is
detected. This helps in eliminating pop or other audio
anomalies.
The ADC has an available zero cross detect (ZCD) that will
The SGTL5000 contains a single stereo DAC that can be
The headphone output can also be driven directly by the
The headphone output is powered by VDDA while the line
The DAC output is routed to the headphone and the
The DAC output has a digital volume control from -90 dB
Stereo headphone outputs are provided which can be
The headphone output has an independent mute that is
The line input is routed to the headphone output by writing
The headphone has an available zero cross detect (ZCD)
Analog Integrated Circuit Device Data
Freescale Semiconductor