SGTL5000XNAA3R2 Freescale, SGTL5000XNAA3R2 Datasheet
SGTL5000XNAA3R2
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SGTL5000XNAA3R2 Summary of contents
Page 1
... I S port to allow routing to Application Processor Integrated Digital Processing • Freescale Surround, Freescale Bass, tone control/ parametric equalizer/graphic equalizer Clocking/Control • PLL allows input of an 8.0 MHz to 27 MHz system clock - Standard audio clocks are derived from PLL Power Supplies • Designed to operate from 1.62 to 3.6 volts ...
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... ADC Control DAC -90dB to 0dB Audio Switch Bass Enhancement Tone Control /GEQ/PEQ Surround +6dB please see Digital Audio Processing section. Headphone Volume Control -52dB to +12dB HP_OUT (CHIP_ANA_HP_CTRL) Line Out Volume Control LINEOUT (CHIP_LINE_OUT_VOL) +12dB Analog Integrated Circuit Device Data Freescale Semiconductor ...
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... VDDA 4 6 HP_L - 7 AGND - 8, 9, 17, 19 VAG 6 11 LINEOUT_R 7 12 LINEOUT_L 8 13 LINEIN_R 9 14 LINEIN_L 10 15 MIC Analog Integrated Circuit Device Data Freescale Semiconductor PIN CONNECTIONS 32 GND 1 HP_R 2 I2S_SCLK 15 GND 3 I2S_LRCLK 14 HP_VGND 4 SYS_MCLK 13 VDDA 5 VDDIO 12 HP_L 6 CPFLT 11 AGND Figure 3. SGTL5000 Pin Connections ...
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... The PAD should be soldered to ground. This is a suggestion for mechanical stability but is not required electrically. Star the ground pins of the chip, VAG ground, and all analog inputs/outputs to a single point, then to the ground plane. 11. Definition Analog Integrated Circuit Device Data Freescale Semiconductor ...
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... Maximum voltage on any analog input RECOMMENDED OPERATING CONDITIONS Digital Voltage (If supplied externally) Digital I/O Voltage Analog Supply Voltage THERMAL RATINGS Storage Temperature Operating Temperature Ambient Analog Integrated Circuit Device Data Freescale Semiconductor ELECTRICAL CHARACTERISTICS MAXIMUM RATINGS Symbol ELECTRICAL CHARACTERISTICS MAXIMUM RATINGS Value V 1.98 DDD V 3 ...
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... Frequency Response PSRR (200 mVp-p @ 1.0 kHz on VDDA) SGTL500 25°C, Slave mode, f DDIO DDA A Symbol = 48 kHz, MCLK = 256 Min Typ Max Unit - 0. RMS kOhm - - ± ±0. 0 RMS - - ±0. 100 - ±0. - ±0. - ±0. Analog Integrated Circuit Device Data Freescale Semiconductor ...
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... THD+N Frequency Response -> DAC -> HEADPHONE OUT - 10 KOHM LOAD SNR (-60 dB input) THD+N Frequency Response PSRR (200 mVp-p @ 1.0 kHz on VDDA) Analog Integrated Circuit Device Data Freescale Semiconductor = 1 1 25°C, Slave mode, f DDIO DDA A Symbol ELECTRICAL CHARACTERISTICS STATIC ELECTRICAL CHARACTERISTICS = 48 kHz, MCLK = 256 f ...
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... S port. The timing applies to all formats. Min Typ Max Unit (2) μs 1.0 – 400 kHz 150 - - ns ns 150 - - ns 125 - - 5 360 - - ns 300 - - ns 100 - - TBD MHz TBD - - TBD - - TBD - -96 kHz - 32*f - kHz LRCLK 64*f LRCLK Analog Integrated Circuit Device Data Freescale Semiconductor ...
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... VDDA VDDIO VDDD (if used) SYS_MCLK CTRL_DATA CTRL_CLK CTRL_ADR0_CS CTRL_CLK Ti2csh CTRL_DATA CTRL_AD0_CS CTRL_CLK CTRL_DATA Analog Integrated Circuit Device Data Freescale Semiconductor TIMING DIAGRAMS Tpc Figure 4. Power Up Timing 1/Fi2c_clk Ti2cdsu Ti2cclkh Ti2cclkl Ti2cdh 2 Figure Timing (CTRL_MODE == 0) Tcsl 1/Fspi_clk Tspiclkh Tspiclkl Tspidsu Tspidh Figure 6 ...
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... ELECTRICAL CHARACTERISTICS TIMING DIAGRAMS . I2S_SCLK I2S_LRCLK In slave mode I2S_LRCLK In master mode I2S_SCLK I2S_DIN I2S_DOUT I2S_LRCLK SGTL500 10 Ti2s_s 1/Fsclk Ti2s_d Ti2s_s Ti2s_h Ti2s_d 1/Flrclk 2 Figure Interface Timing Analog Integrated Circuit Device Data Freescale Semiconductor ...
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... It is designed to provide a complete audio solution for portable products needing line-in, mic-in, line-out, headphone-out, and digital I/O. Deriving it’s architecture from best in class Freescale integrated products that are currently on the market, the SGTL5000 is able to achieve ultra low power with very high performance and functionality, all in one of the smallest footprints available ...
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... The SGTL5000 supports various combinations of SYS_MCLK frequency and sampling frequency as shown in Table 6. Using a synchronous SYS_MCLK allows for lower power as the internal PLL is not used. Chip Powerup and Supply Configurations. Dynamic Electrical 2 S port clocks. This allows Analog Integrated Circuit Device Data Freescale Semiconductor ...
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... CHIP_PLL_CTRL->FRAC_DIVISOR = ((196.608 MHz/ 12 MHz) - 16) * 2048 = 786 (decimal) Refer to PLL programming PLL Configuration. Analog Integrated Circuit Device Data Freescale Semiconductor FUNCTIONAL INTERNAL BLOCK DESCRIPTION SUPPORTED RATES 256, 384, 512 8, 11.025, 16, 22.5, 32, 44.1, 48, 96 clock from the system processor could be used as the clock input to the SGTL5000 ...
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... The headphone has an available zero cross detect (ZCD) which, as previously described, will prevent any volume change until a zero-volt crossing of the audio signal is detected. This helps in eliminating pop or other audio anomalies. Analog Integrated Circuit Device Data Freescale Semiconductor ...
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... The line outputs also have a dedicated mute that is controlled by the register field CHIP_ANA_CTRL- >MUTE_LO. Analog Integrated Circuit Device Data Freescale Semiconductor FUNCTIONAL DESCRIPTION FUNCTIONAL INTERNAL BLOCK DESCRIPTION The line out volume is intended as maximum output level adjustment intended to be used to set the maximum output swing ...
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... CHIP_I2S_CTRL POWER (MW) V DDIO 0.9 6.19 0.9 8.08 1.10 8.67 1.06 6.02 0.89 4.27 0.002 0.038 2.17 9.31 POWER(MW) V DDIO 0.067 11.60 0.067 15.03 0.343 16.53 0.296 10.56 0.039 6.43 0.002 0.139 2.76 22.05 Analog Integrated Circuit Device Data Freescale Semiconductor ...
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... SCLKFREQ = 0; SCLK_INV = 0; DLEN = 1; I2S_MODE = 1; LRALIGN = 1; LRPOL = 0) I2S_LRCLK I2S_SCLK I2S_DIN, DOUT Analog Integrated Circuit Device Data Freescale Semiconductor SGTL5000 can only operate in synchronous mode (see Clocking) while master mode, the clocks will be synchronous to SYS_MCLK or the output of the PLL when the part is running in asynchronous mode ...
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... n-1) 0 Figure 11. PCM Formats • Freescale Surround • Freescale Bass Enhancement • 7-Band Parameter EQ / 5-Band Graphic EQ / Tone Control (only one can be used at a time) • Automatic Volume Control (AVC) The block diagram in which the signal passes through these blocks Mode. ...
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... Dual Input Mixer how to enable/disable the mixer and also to set the main and mix channel volume. Freescale Surround Freescale Surround is a royalty free virtual surround algorithm for stereo or mono inputs. It widens and deepens sound stage for music input. FUNCTIONAL DEVICE OPERATION ...
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... DAP_SGTL_SURROUND -> WIDTH_CONTROL ->SELECT Freescale Bass Enhance Freescale Bass Enhance is a royalty-free algorithm that enhances natural bass response of the audio. Bass Enhance extracts bass content from right and left channels, adds bass and mixes this back up with the original signal. An optional complementary high pass filter is provided after the mixer. ...
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... Classical, etc, the coefficients must be calculated, converted to 20-bit hex values and written to the registers. Note that coefficients are sample-rate dependent and separate coefficients must be generated for different sample rates. Please contact Freescale for assistance with generating the coefficients. Refer to 7-Band PEQ Preset Selection example that shows how load the filter coefficients when the end-user changes the preset ...
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... Figure 17. Functional I C Diagram Output To SGTL Surround interface is used to read and write 2 C device 2 C address 2 C transaction looks as follows write transaction follows: 2 shows the functional I C timing diagram. ACK ACK D15 D8 ACK D7 D0 Stop Condition Analog Integrated Circuit Device Data Freescale Semiconductor 2 C ...
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... MOSI Figure 18. Functional Timing Diagram of SPI Protocol Analog Integrated Circuit Device Data Freescale Semiconductor white fields are the SGTL5000 responses. Data [n] corresponds to the data read from the address sent, data[n+1] is the data from the next register, and so on Start Condition ...
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... Enable short detect mode for headphone left/right // and center channel and set short detect current trip level // Write CHIP_SHORT_CTRL // Enable Zero-cross detect if needed for HP_OUT (bit 5) and ADC (bit 1) 0x0008 0x7260 0x4260 0x4A60 0x006C 0x004F 0x1106 Analog Integrated Circuit Device Data Freescale Semiconductor ...
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... Configure mix channel volume to 50% (attenuate the mix // input level by half) Write DAP_MIX_CHAN 0x4000 Freescale Surround The Freescale Surround on/off function will be typically controlled by the end-user. End-user driven programming steps are shown in The default WIDTH_CONTROL of 4 should be appropriate for most applications. This optional programming step shows how to configure a different width value ...
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... Least width, 0x7 = Most width). This example shows // a width setting of 5 Modify DAP_SGTL_SURROUND->WIDTH_CONTROL 0x0005 // bits 6:4 Freescale Bass Enhance The Freescale Bass Enhance on/off function will be typically controlled by the end-user. End-user driven programming steps are shown in End-user Driven Chip Configuration. ...
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... Write DAP_AUDIO_EQ_TREBLE_BAND4 usCurrentVal; } FREESCALE SURROUND ON/OFF This programming example shows how to program the Surround when end-user turns it on/off on his device. The Surround width should be ramped up to highest value before enabling/disabling the Surround to avoid any pops. // Read current Surround width value // WIDTH_CONTROL bits 6:4 usOriginalVal = (Read DAP_SGTL_SURROUND > ...
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... AVC on/off when end-user turns it on/off on his device. // Enable AVC (To disable, write 0x0000) Modify DAP_AVC_CTRL->EN 0x0001 // bit 0 Register description CHIP_ID RESET SGTL5000 Part ID 0xA0 0xA0 - 8 bit identifier for SGTL5000 SGTL5000 Revision ID 0x00 0xHH - revision number for SGTL5000. 0x0000 REVID DEFINITION Analog Integrated Circuit Device Data Freescale Semiconductor 0 ...
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... DAC_POWERUP RW 4 DAP_POWERUP RW 3:2 RSVD RW 1 I2S_OUT_POWERUP RW 0 I2S_IN_POWERUP RW Analog Integrated Circuit Device Data Freescale Semiconductor RESET Reserved 0x0 Enable/disable the ADC block, both digital and analog 0x0 0x0 = Disable 0x1 = Enable Enable/disable the DAC block, both analog and digital 0x0 ...
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... Before this field is set to 0x3 (Use PLL), the PLL must be powered up by setting CHIP_ANA_POWER->PLL_POWERUP and CHIP_ANA_POWER- >VCOAMP_POWERUP. Also, the PLL dividers must be calculated based on the external MCLK rate and CHIP_PLL_CTRL register must be set (see CHIP_PLL_CTRL register description details on how to calculate the divisors SYS_FS MCLK_FREQ Analog Integrated Circuit Device Data Freescale Semiconductor 0 ...
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... I2S_MODE RW 0x0 1 LRALIGN RW 0x0 0 LRPOL RW 0x0 Analog Integrated Circuit Device Data Freescale Semiconductor DEFINITION Reserved Sets frequency of I2S_SCLK when in master mode (MS=1). When in slave mode (MS=0), this field must be set appropriately to match SCLK input rate. 0x0 = 64Fs 0x1 = 32Fs - Not supported for RJ mode (I2S_MODE = 1) Configures master or slave of I2S_LRCLK and I2S_SCLK ...
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... Select data source for DAC 0x1 0x0 = ADC 0x1 = I2S_IN 0x2 = Reserved 0x3 = DAP Reserved 0x0 Select data source for I2S_DOUT 0x0 0x0 = ADC 0x1 = I2S_IN 0x2 = Reserved 0x3 = DAP DAC_SELECT RSVD I2S_SELECT DEFINITION Analog Integrated Circuit Device Data Freescale Semiconductor 0 ...
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... RSVD RW 3 DAC_MUTE_RIGHT RW 2 DAC_MUTE_LEFT RW 1 ADC_HPF_FREEZE RW 0 ADC_HPF_BYPASS RW Analog Integrated Circuit Device Data Freescale Semiconductor RSVD RESET Reserved 0x0 Volume Busy DAC Right 0x0 0x0 = Ready 0x1 = Busy - This indicates the channel has not reached its programmed volume/mute level Volume Busy DAC Left ...
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... Sets drive strength for output pads per the table below. VDDIO 1.8 V 2.5 V 0x0 = Disable 0x1 = 1.66 mA 2.87 mA 0x2 = 3.33 mA 5.74 mA 0x3 = 4. DAC_VOL_LEFT DEFINITION I2S_DOUT CTRL_DATA CTRL_CLK DEFINITION 3.3 V 4.02 mA 8.03 mA 12.05 mA 3.3 V 4.02 mA 8.03 mA 12.05 mA Analog Integrated Circuit Device Data Freescale Semiconductor 0 0 ...
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... BITS FIELD RW 5:4 I2S_DOUT RW 3:2 CTRL_DATA RW 1:0 CTRL_CLK RW Analog Integrated Circuit Device Data Freescale Semiconductor RESET DOUT Pad Drive Strength 0x1 Sets drive strength for output pads per the table below. VDDIO 1.8 V 2.5 V 0x0 = Disable 0x1 = 1.66 mA 2.87 mA 0x2 = 3. ...
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... This range will be -6 +16 ADC_VOL_M6DB is set to 1. ADC Left Channel Volume 0x0 Left channel analog ADC volume control in 1.5 dB steps. 0x0 = 0 dB 0x1 = +1.5 dB ... 0xF = +22.5 dB This range will be -6 +16 ADC_VOL_M6DB is set ADC_VOL_LEFT DEFINITION Analog Integrated Circuit Device Data Freescale Semiconductor 0 ...
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... RSVD RO 8 MUTE_LO RW 7 RSVD RO 6 SELECT_HP RW 5 EN_ZCD_HP RW Analog Integrated Circuit Device Data Freescale Semiconductor RSVD DEFINITION Reserved 0x0 Headphone Right Channel Volume 0x18 Right channel headphone volume control with 0.5 dB steps. 0x00 = +12 dB 0x01 = +11.5 dB 0x18 = 0 dB ... ...
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... VDDC_MAN_ASSN should be used to manually assign VDDIO as the source for chargepump. Reserved 0x0 Sets the VDDD lin. regulator output voltage steps. Must clear pwd_linreg_d 0x0 bit to enable this lin reg. 0x0 = 1.60 0xF = 0.85 DEFINITION RSVD D_PROGRAMMING DEFINITION Analog Integrated Circuit Device Data Freescale Semiconductor 0 ...
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... RW 15:9 RSVD RO 8:4 VAG_VAL RW 3:1 BIAS_CTRL RW 0 SMALL_POP RW Analog Integrated Circuit Device Data Freescale Semiconductor register controls VAG_VAL RESET Reserved 0x0 Analog Ground Voltage Control 0x0 These bits control the analog ground voltage steps. This should usually be set to VDDA/2 or lower for best performance (maximum output swing at minimum THD) ...
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... Sets the microphone amplifier gain setting the THD can be slightly higher than other paths- typically around ~65 dB. At other gain settings the THD will be better. 0x0 = 0 dB 0x1 = +20 dB 0x2 = +30 dB 0x3 = + RSVD GAIN DEFINITION Analog Integrated Circuit Device Data Freescale Semiconductor 0 ...
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... Table 30. Line Out Output Level Values VDDA VAG_VAL 1.8 V 0.9 1.8 V 0.9 3.3 V 1.55 3.3 V 1.55 Analog Integrated Circuit Device Data Freescale Semiconductor OUT_CURRENT RSVD RESET Reserved 0x0 Controls the output bias current for the lineout amplifiers. The nominal recommended 0x0 setting for a 10 kohm load with 1 ...
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... When cleared, the PLL will be turned off. This must be set before CHIP_CLK_CTRL - > MCLK_FREQ is programmed to 0x3. The CHIP_PLL_CTRL register must be configured correctly before setting this bit. Power up the primary VDDD linear regulator. 0x0 0x0 = Power down 0x1 = Power DEFINITION Analog Integrated Circuit Device Data Freescale Semiconductor 0 ...
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... NE_POWERUP 1 ADC_POWERUP RW 0 LINEOUT_POWERUP RW Analog Integrated Circuit Device Data Freescale Semiconductor RESET Power up the PLL VCO amplifier. 0x0 0x0 = Power down 0x1 = Power up Power up the VAG reference buffer. Setting this bit starts the power up ramp for the 0x0 headphone and lineout. The headphone (and/or lineout) powerup should be set BEFORE clearing this bit ...
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... PLL_OUTPUT_FREQ = 180.6336 MHz if System sample rate = 44.1 kHz else PLL_OUTPUT_FREQ = 196.608 MHz if System sample rate!= 44.1 kHz INPUT_FREQ = Frequency of the external MCLK provided if CHIP_CLK_TOP_CTRL- >INPUT_FREQ_DIV2 = 0x0 else INPUT_FREQ = (Frequency of the external MCLK provided/2) If CHIP_CLK_TOP_CTRL->INPUT_FREQ_DIV2 = 0x1 DEFINITION Analog Integrated Circuit Device Data Freescale Semiconductor 0 ...
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... ENABLE_INT_OSC RW 10:4 RSVD RW 3 INPUT_FREQ_DIV2 RW 2:0 RSVD RW Analog Integrated Circuit Device Data Freescale Semiconductor has the RSVD RESET Reserved 0x0 Setting this bit enables an internal oscillator to be used for the zero cross detectors, 0x0 the short detect recovery, and the charge pump. This will allow the I off while still operating an analog signal path ...
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... These bits control the bias current for the first stage of the headphone amplifier. 0x0=nominal, 0x1=-50%, 0x2=+100%, 0x3=+50% 0x0 These bits control the headphone output current in classA mode and also the pull-down strength while powering off. These bits will normally not be needed RSVD DEFINITION DEFINITION Analog Integrated Circuit Device Data Freescale Semiconductor 0 0 ...
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... RW TIMING 7 DAC_EXTEND_RTZ RW Analog Integrated Circuit Device Data Freescale Semiconductor RESET 0x1 This defaults high. When this bit is high the headphone is in classAB mode. ClassA mode would normally not be used. 0x1 This defaults high. When this bit is high and the capless headphone center channel is powered off the output will be tied to ground ...
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... Change the clock edge used for the ADC sampling. 0x0 Change the clock edge used for the analog to digital ADC data crossing 0x0 Drops ADC bias currents by 20% 0x0 Turns off the ADC dithering. 0x0 DEFINITION Analog Integrated Circuit Device Data Freescale Semiconductor ...
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... LVLADJR RW 11 RSVD RO 10:8 LVLADJL RW 7 RSVD RO 6:4 LVLADJC RW Analog Integrated Circuit Device Data Freescale Semiconductor register LVLADJL RSVD LVLADJC RESET Reserved 0x0 These bits adjust the sensitivity of the right channel headphone short detector 0x0 steps.This trip point can vary by ~30% over process so leave plenty of guard band to avoid false trips. This short detect trip point is also effected by the bias current adjustments made by CHIP_REF_CTRL -> ...
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... Enable/Disable digital audio processing (DAP) 0x0 0x0 = Disable. When disabled, no audio will pass-through. 0x1 = Enable. When enabled, audio can pass-through DAP even if none of the DAP functions are enabled. DEFINITION MIX_EN RSVD DAP_EN DEFINITION Analog Integrated Circuit Device Data Freescale Semiconductor 0 ...
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... RO 8 BYPASS_HPF RW 7 RSVD RO 6:4 CUTOFF RW 3:1 RSVD Analog Integrated Circuit Device Data Freescale Semiconductor RSVD RESET Reserved 0x0 Set to Enable the PEQ filters 0x0 0x0 = Disabled 0x1 = 1 Filter Enabled 0x2 = 2 Filters Enabled ..... 0x7 = Cascaded 7 Filters DAP_AUDIO_EQ->EN bit must be set order to enable the PEQ ...
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... SGTL Surround Width Control - The width control changes the perceived width of the 0x4 sound field. 0x0 = Least Width ...... 0x7 = Most Width Reserved 0x0 SGTL Surround Selection 0x0 0x0 = Disabled 0x1 = Disabled 0x2 = Mono input Enable 0x3 = Stereo input Enable DEFINITION DEFINITION RSVD SELECT DEFINITION Analog Integrated Circuit Device Data Freescale Semiconductor ...
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... BITS FIELD RW 15:9 RSVD 7:0 INDEX RW Analog Integrated Circuit Device Data Freescale Semiconductor RESET Reserved 0x0 When set, the coefficients written in the ten coefficient data registers will be loaded into 0x0 the filter specified by INDEX Specifies the index for each of the seven bands of the filter coefficient that needs to be 0x0 written to ...
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... RSVD RESET 0x0 0x0 0x0 0x0 Least significant 4 bits of the 20-bit filter coefficient that needs to be written. 0x0 BIT_8 BIT_7 BIT_6 BIT_5 BIT_4 DEFINITION BIT_3 BIT_2 BIT_1 BIT_0 DEFINITION Analog Integrated Circuit Device Data Freescale Semiconductor 0 0 ...
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... RSVD BITS FIELD RW 15:7 RSVD RO 6:0 VOLUME RW Analog Integrated Circuit Device Data Freescale Semiconductor RESET Reserved 0x0 Sets Tone Control Bass/GEQ Band0 0x2F 0x5F = sets 0x2F = sets 0x00 = sets to -12 dB Each LSB is 0.25 dB. To convert dB to hex value, use: Hex Value = 4* dBValue + 47 ...
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... Each LSB is 0.25 dB. To convert dB to hex value, use: Hex Value = 4* dBValue + VOL RESET DAP Main Channel Volume 0x8000 0xFFFF = 200% 0x8000 (default) = 100% 0x0000 = VOL RESET DAP Mix Channel Volume 0x0000 0xFFFF = 200% 0x8000 = 100% 0x0000 (default DEFINITION VOLUME DEFINITION DEFINITION Analog Integrated Circuit Device Data Freescale Semiconductor ...
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... RSVD RO 9:8 LBI_RESPONSE RW 7:6 RSVD RO 5 HARD_LIMIT_EN RW 4:1 RSVD Analog Integrated Circuit Device Data Freescale Semiconductor LBI_RESPONSE RSVD RESET Reserved 0x0 Reserved. 0x1 Maximum gain that can be applied by the AVC in expander mode. 0x1 0x0 = 0 dB gain 0x1 = 6 gain 0x2 = gain Reserved ...
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... Hex Value = (1 - (10^(-(Rate_dBs/(20*SYS_FS)))) * 2^23 where, SYS_FS is the system sample rate configured in CHIP_CLK_CTRL register. Example values: 0x284 = 32 dB/s 0xA0 = 8.0 dB/s 0x50 = 4.0 dB/s 0x28 = 2.0 dB DEFINITION DEFINITION DEFINITION Analog Integrated Circuit Device Data Freescale Semiconductor ...
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... MSB RW Table 63. DAP_COEF_WR_A1_LSB 0x0136 BITS FIELD RW 15:4 RSVD RO 3:0 LSB RW Analog Integrated Circuit Device Data Freescale Semiconductor MSB RESET Most significant 16-bits of the 20-bit filter coefficient that needs to be written 0x0 RSVD RESET Reserved 0x0 Least significant 4 bits of the 20-bit filter coefficient that needs to be written. ...
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... MSB RESET Most significant 16-bits of the 20-bit filter coefficient that needs to be written 0x0 RSVD RESET Reserved 0x0 Least significant 4 bits of the 20-bit filter coefficient that needs to be written. 0x0 DEFINITION LSB DEFINITION Analog Integrated Circuit Device Data Freescale Semiconductor 0 0 ...
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... Figure 19. SGTL5000 Typical Application Schematic for 20 QFN Analog Integrated Circuit Device Data Freescale Semiconductor TYPICAL APPLICATIONS INTRODUCTION although it should be noted that all configurations offer a low cost design with high performance and low power. ...
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... TYPICAL APPLICATIONS INTRODUCTION Figure 20. SGTL5000 Lowest Power Application Schematic for 20 QFN SGTL500 62 Analog Integrated Circuit Device Data Freescale Semiconductor ...
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... Figure 21. SGTL5000 Typical Application Schematic for 32 QFN Analog Integrated Circuit Device Data Freescale Semiconductor TYPICAL APPLICATIONS INTRODUCTION SGTL5000 63 ...
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... XVLQJ WKH VDPH YROWDJH WKLV DOORZV UHPRYDO RI SRZHU GHFRXSOLQJ FDS %\ XVLQJ D YROWDJH DERYH &3),/7 FDQ EH UHPRYHG Figure 22. SGTL5000 Lowest Cost Application Schematic for 32 QFN SGTL500 64 ) 6ROGHU 3DG WR * QHHG IRU H[WHUQDO FDS 9 WKH &$3 FRQQHFWHG WR 9 Analog Integrated Circuit Device Data Freescale Semiconductor ...
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... Figure 23. SGTL5000 Lowest Power Application Schematic for 32 QFN Analog Integrated Circuit Device Data Freescale Semiconductor 6ROGHU 3DG WR * 9''' LV GULYHQ H[WHUQDOO VXSSO\ 9''$ LV GULYHQ DW 9 9'',2 LV GULYHQ DW 9 TYPICAL APPLICATIONS INTRODUCTION SGTL5000 65 ...
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... PACKAGING PACKAGE DIMENSIONS For the most current package revision, visit www.freescale.com and perform a keyword search using the 98Axxxxxxxxx listed on the following pages. SGTL500 66 PACKAGING PACKAGE DIMENSIONS EP SUFFIX 20-PIN 98ARE10742D REVISION 0 Analog Integrated Circuit Device Data Freescale Semiconductor ...
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... Analog Integrated Circuit Device Data Freescale Semiconductor EP SUFFIX 20-PIN 98ARE10742D REVISION 0 PACKAGING PACKAGE DIMENSIONS SGTL5000 67 ...
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... PACKAGING PACKAGE DIMENSIONS SGTL500 68 EP SUFFIX 20-PIN 98ARE10742D REVISION 0 Analog Integrated Circuit Device Data Freescale Semiconductor ...
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... Analog Integrated Circuit Device Data Freescale Semiconductor FC SUFFIX 32-PIN 98ARE10739D REVISION 0 PACKAGING PACKAGE DIMENSIONS SGTL5000 69 ...
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... PACKAGING PACKAGE DIMENSIONS SGTL500 70 FC SUFFIX 32-PIN 98ARE10739D REVISION 0 Analog Integrated Circuit Device Data Freescale Semiconductor ...
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... Analog Integrated Circuit Device Data Freescale Semiconductor FC SUFFIX 32-PIN 98ARE10739D REVISION 0 PACKAGING PACKAGE DIMENSIONS SGTL5000 71 ...
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... REVISION HISTORY REVISION DATE DESCRIPTION • Conversion from the old Freescale form and style to the current version. No existing content has been 3.0 6/2010 added, altered, or removed. • Corrected Pin 4 explanation (32-pin package) and added Pin 3 (32-Pin package) to Table 1. 4.0 9/2010 SGTL500 ...
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... Freescale Semiconductor was negligent regarding the design or manufacture of the part. Freescale™ and the Freescale logo are trademarks of Freescale Semiconductor, Inc ...