SGTL5000XNAA3 Freescale, SGTL5000XNAA3 Datasheet - Page 31

• Manufacturer Part Number: SGTL5000XNAA3
• Manufacturer: Freescale

Specifications of SGTL5000XNAA3

• Single Supply Voltage (typ): 1.8/2.5/3.3V
• Lead Free Status / RoHS Status: Compliant

Table 17. CHIP_I2S_CTRL 0x0006
Analog Integrated Circuit Device Data
Freescale Semiconductor
BITS
15:9
5:4
3:2
15
8
7
6
1
0
14
SCLKFREQ
I2S_MODE
SCLK_INV
LRALIGN
LRPOL
FIELD
RSVD
DLEN
MS
13
RSVD
12
RW
RW
RW
RW
RW
RW
RW
RW
RO
11
RESET
0x0
0x0
0x0
0x0
0x1
0x0
0x0
0x0
10
Reserved
Sets frequency of I2S_SCLK when in master mode (MS=1). When in slave mode (MS=0),
this field must be set appropriately to match SCLK input rate.
0x0 = 64Fs
0x1 = 32Fs - Not supported for RJ mode (I2S_MODE = 1)
Configures master or slave of I2S_LRCLK and I2S_SCLK. 0x0 = Slave: I2S_LRCLK and
I2S_SCLK are inputs
0x1 = Master: I2S_LRCLK and I2S_SCLK are outputs
NOTE: If the PLL is used (CHIP_CLK_CTRL->MCLK_FREQ==0x3), the SGTL5000 must
be a master of the I
Sets the edge that data (input and output) is clocked in on for I2S_SCLK
0x0 = data is valid on rising edge of I2S_SCLK
0x1 = data is valid on falling edge of I2S_SCLK
I
0x0 = 32 bits (only valid when SCLKFREQ=0), not valid for Right Justified Mode
0x1 = 24 bits (only valid when SCLKFREQ=0)
0x2 = 20 bits
0x3 = 16 bits
Sets the mode for the I
0x0 = I
0x1 = Right Justified Mode
0x2 = PCM Format A/B
0x3 = RESERVED
I2S_LRCLK Alignment to data word. Not used for Right Justified mode
0x0 = Data word starts 1 I2S_SCLK delay after I2S_LRCLK transition (I
format A)
0x1 = Data word starts after I2S_LRCLK transition (left justified format, PCM format B)
I2S_LRCLK Polarity when data is presented.
0x0 = I2S_LRCLK = 0 - Left, 1 - Right
1x0 = I2S_LRCLK = 0 - Right, 1 - Left
The left subframe should be presented first regardless of the setting of LRPOL.
2
S data length
9
2
S mode or Left Justified (Use LRALIGN to select)
8
2
S port (MS==1)
MS
2
7
S port
6
DEFINITION
5
DLEN
4
FUNCTIONAL DEVICE OPERATION
I2S_MODE
3
PROGRAMMING EXAMPLES
2
2
S format, PCM
1
SGTL5000
LRPOL
0
31