AD9891KBCZ Analog Devices Inc, AD9891KBCZ Datasheet - Page 35
AD9891KBCZ
Manufacturer Part Number
AD9891KBCZ
Description
Manufacturer
Analog Devices Inc
Datasheet
1.AD9891KBCZ.pdf
(58 pages)
Specifications of AD9891KBCZ
Analog Front End Type
CCD
Analog Front End Category
Video
Interface Type
Serial (3-Wire)
Operating Supply Voltage (min)
2.7/3V
Resolution
10b
Number Of Adc's
1
Power Supply Type
Analog/Digital
Operating Temp Range
-20C to 85C
Operating Temperature Classification
Commercial
Mounting
Surface Mount
Pin Count
64
Package Type
CSPBGA
Number Of Channels
1
Lead Free Status / RoHS Status
Compliant
POWER-DOWN MODE OPERATION
The AD9891/AD9895 contain three different power-down
modes to optimize the overall power dissipation in a particular
application. Bits [1:0] of the OPRMODE Register control the
power-down state of the device:
OPR_MODE [1:0] = 00 = Normal Operation (full power)
OPR_MODE[1:0] = 01 = Power-Down 1 Mode
OPR_MODE[1:0] = 10 = Power-Down 2 Mode
OPR_MODE[1:0] = 11 = Power-Down 3 Mode (lowest
overall power)
REV. A
(PIXEL COUNTER)
NOTES
1. INTERNAL H-COUNTER IS RESET 8 CLOCK CYCLES AFTER THE HD FALLING EDGE.
2. PxGA STEERING IS SYNCHRONIZED WITH THE RESET OF THE INTERNAL H-COUNTER (MOSAIC SEPARATE MODE IS SHOWN).
H124, RG, V1–V4,
H-COUNTER
PxGA GAIN
REGISTER
NOTES
1. SYNC RISING EDGE RESETS VD/HD AND COUNTERS TO ZERO.
2. SYNC POLARITY IS PROGRAMMABLE USING SYNCPOL REGISTER (ADDR x025).
3. DURING SYNC LOW, ALL INTERNAL COUNTERS ARE RESET AND VD/HD CAN BE SUSPENDED USING THE SYNCSUSPEND REGISTER (ADDR x026).
4. IF SYNCSUSPEND = 1, VERTICAL CLOCKS AND H1–H2, RG ARE HELD AT THEIR DEFAULT POLARITIES.
5. IF SYNCSUSPEND = 0, THEN ALL CLOCK OUTPUTS CONTINUE TO OPERATE NORMALLY UNTIL SYNC RESET EDGE.
VSG, SUBCK
CLI
HD
VD
SYNC
VD
HD
X
X
Figure 44. External VD/HD and Internal H-Counter Synchronization, SLAVE Mode
X
X
X
X
3ns MIN
Figure 43. SYNC Timing to Synchronize AD989x with External Timing
X
X
X
X
X
X
X
X
X
X
H-COUNTER
RESET
X
X
0
0
1
1
2
0
–35–
3
1
SUSPEND
0
4
Table XVI summarizes the operation of each power-down mode.
Note that in any mode, the OUT_CONT Register takes priority
over the power-down modes where the digital output states are
concerned. Power-Down 3 Mode has the lowest power consump-
tion, and it even powers down the crystal oscillator circuit
between CLI and CLO. Thus, if CLI and CLO are being used
with a crystal to generate the master clock, this circuit will be
powered down and there will be no clock signal. When returning
from Power-Down 3 Mode to normal operation, the timing core
must be reset at least 500 ms after the OPR_MODE Register is
written to. This will allow sufficient time for the crystal circuit
to settle.
1
5
0
6
7
1
8
0
1
9
10
0
11
1
12
0
13
AD9891/AD9895
1
14
0
2
0
1
3
2
2
3
3
4