AD9891KBCZ Analog Devices Inc, AD9891KBCZ Datasheet - Page 11

• Manufacturer Part Number: AD9891KBCZ
• Manufacturer: Analog Devices Inc

Specifications of AD9891KBCZ

• Analog Front End Type: CCD
• Analog Front End Category: Video
• Interface Type: Serial (3-Wire)
• Operating Supply Voltage (min): 2.7/3V
• Resolution: 10b
• Number Of Adc's: 1
• Power Supply Type: Analog/Digital
• Operating Temp Range: -20C to 85C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 64
• Package Type: CSPBGA
• Number Of Channels: 1
• Lead Free Status / RoHS Status: Compliant

SYSTEM OVERVIEW
Figure 5 shows the typical system block diagram for the AD9891/
AD9895 used in Master Mode. The CCD output is processed by
the AD9891/AD9895’s AFE circuitry, which consists of a CDS,
PxGA, VGA, black level clamp, and an A/D converter. The digi-
tized pixel information is sent to the digital image processor chip,
which performs the post-processing and compression. To operate
the CCD, all CCD timing parameters are programmed into the
AD9891/AD9895 from the system microprocessor, through the
3-wire serial interface. From the system master clock, CLI, pro-
vided by the image processor or external crystal, the AD9891/
AD9895 generates all of the CCD’s horizontal and vertical clocks
and all internal AFE clocks. External synchronization is provided
by a SYNC pulse from the microprocessor, which will reset
internal counters and resync the VD and HD outputs.
Alternatively, the AD9891/AD9895 may be operated in Slave
Mode, in which the VD and HD are provided externally from
the image processor. In this mode, all AD9891/AD9895 timing
will be synchronized with VD and HD.
REV. A
Figure 5. Typical System Block Diagram, Master Mode
CCD
H1–H4, RG, VSUB
STROBE
V-DRIVER
MSHUT
CCDIN
INTERFACE
SERIAL
V1–V4, VSG1–VSG8, SUBCK
AD989x
P
SYNC
CLPOB/PBLK
HD, VD
LD/FD
DOUT
DCLK
CLI
PROCESSING
DIGITAL
IMAGE
ASIC
–11–
The H-drivers for H1–H4 and RG are included in the AD9891/
AD9895, allowing these clocks to be directly connected to the CCD.
H-drive voltage of up to 5 V is supported. An external V-driver is
required for the vertical transfer clocks, the sensor gate pulses,
and the substrate clock.
The AD9891/AD9895 also includes programmable MSHUT
and STROBE outputs, which may be used to trigger mechani-
cal shutter and strobe (flash) circuitry.
Figure 6 shows the horizontal and vertical counter dimensions
for the AD9891/AD9895. All internal horizontal and vertical
clocking is programmed using these dimensions to specify line
and pixel locations.
Figure 6. Vertical and Horizontal Counters
MAXIMUM
FIELD
DIMENSIONS
12-BIT HORIZONTAL = 4096 PIXELS MAX
12-BIT VERTICAL = 4096 LINES MAX
AD9891/AD9895