ADV7314KST Analog Devices Inc, ADV7314KST Datasheet - Page 22

• Manufacturer Part Number: ADV7314KST
• Manufacturer: Analog Devices Inc

Specifications of ADV7314KST

• Number Of Dac's: 6
• Adc/dac Resolution: 14b
• Screening Level: Commercial
• Package Type: LQFP
• Pin Count: 64
• Lead Free Status / RoHS Status: Compliant

ADV7314
NOTES
1
2
SR7-
SR0
12h
13h
14h
15h
When set to 0, the line and field counters automatically wrap around at the end of the field/frame of the standard selected. When set to 1 , the field/line
counters are free running and wrap around when external sync signals indicate so.
Adaptive Filter mode is not available in PS only @ 54 MHz input mode.
Register
HD Mode
Register 3
HD Mode
Register 4
HD Mode
Register 5
HD Mode
Register 6
Bit Description
HD Y Delay with
Respect to Falling Edge
of HSYNC
HD with Respect to
Falling Edge of HSYNC
HD CGMS
HD CGMS CRC
HD Cr/Cb Sequence
Reserved
HD Input Format
Sinc Filter on DAC D,
E, F
Reserved
HD Chroma SSAF
HD Chroma Input
HD Double Buffering
HD Timing Reset
1080i Frame Rate
Reserved
HD VSYNC/Field
Input
Lines/Frame
Reserved
HD RGB Input
HD Sync on PrPb
HD Color DAC Swap
HD Gamma Curve A/B
HD Gamma Curve
Enable
HD Adaptive Filter
Mode
HD Adaptive Filter
Enable
2
2
1
Bit 7
0
1
0
1
0
1
0
1
Bit 6 Bit 5
0
1
0
1
0
1
0
1
0
0
0
0
1
0
1
0
0
1
Bit 4
0
0
1
1
0
0
0
0
1
Bit 3 Bit 2
0
1
0
1
0
0
1
0
0
1
–22–
0
0
0
0
1
0
1
0
0
0
1
Bit 1
0
0
1
1
0
0
0
1
0
1
Bit 0
0
1
0
1
0
0
1
x
0
Register Setting
0 clk cycle
1 clk cycle
2 clk cycle
3 clk cycle
4 clk cycle
0 clk cycle
1 clk cycle
2 clk cycle
3 clk cycle
4 clk cycle
Disabled
Enabled
Disabled
Enabled
Cb after falling edge of HSYNC
Cr after falling edge of HSYNC
0 must be written to this bit
8-bit input
10-bit input
Disabled
Enabled
0 must be written to this bit
Disabled
Enabled
4:4:4
4:2:2
Disabled
Enabled
A low-high-low transition resets the
internal HD timing counters
30 Hz/2200 total samples/line
25 Hz/2640 total samples/line
0 should be written to these bits
Field Input
VSYNC Input
Update Field/line counter
Field/line counter free running
0 must be written to this bit
Disabled
Enabled
Disabled
Enabled
DAC E = Pb; DAC F = Pr
DAC E = Pr; DAC F = Pb
Gamma Curve A
Gamma Curve B
Disabled
Enabled
Mode A
Mode B
Disabled
Enabled
Reset Value
00h
4Ch
00h
00h
REV. 0