STK14C88-3WF35 Cypress Semiconductor Corp, STK14C88-3WF35 Datasheet - Page 3

• Manufacturer Part Number: STK14C88-3WF35
• Description: STK14C88-3WF35
• Manufacturer: Cypress Semiconductor Corp

Specifications of STK14C88-3WF35

• Format - Memory: RAM
• Memory Type: NVSRAM (Non-Volatile SRAM)
• Memory Size: 256K (32K x 8)
• Speed: 35ns
• Interface: Parallel
• Voltage - Supply: 4.5 V ~ 5.5 V
• Operating Temperature: 0°C ~ 70°C
• Package / Case: 32-DIP (0.600", 15.24mm)
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Pin Configurations
Table 1. Pin Definitions - 32-Pin SOIC/32-Pin PDIP
Document Number: 001-50592 Rev. *A
Pin Name
DQ
A
V
HSB
0
V
V
WE
OE
CE
0
–A
CAP
SS
CC
-DQ
14
7
Alt
W
G
E
Power Supply Power Supply Inputs to the Device.
Power Supply AutoStore Capacitor. Supplies power to nvSRAM during power loss to store data from
I/O Type
Input or
Input or
Ground
Output
Output
Input
Input
Input
Input
Figure 1. Pin Diagram - 32-Pin SOIC/32-Pin PDIP
Address Inputs. Used to select one of the 32,768 bytes of the nvSRAM.
Bidirectional Data I/O lines. Used as input or output lines depending on operation.
Write Enable Input, Active LOW. When the chip is enabled and WE is LOW, data on the
I/O pins is written to the specific address location.
Chip Enable Input, Active LOW. When LOW, selects the chip. When HIGH, deselects the
chip.
Output Enable, Active LOW. The active LOW OE input enables the data output buffers
during read cycles. Deasserting OE HIGH causes the I/O pins to tristate.
Ground for the Device. The device is connected to ground of the system.
Hardware Store Busy (HSB). When LOW, this output indicates a Hardware Store is in
progress. When pulled low external to the chip, it initiates a nonvolatile STORE operation. A
weak internal pull up resistor keeps this pin high if not connected (connection optional).
SRAM to nonvolatile elements.
Description
STK14C88-3
Page 3 of 17
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