PIC18LF8628T-I/PT Microchip Technology, PIC18LF8628T-I/PT Datasheet - Page 9

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PIC18LF8628T-I/PT

Manufacturer Part Number
PIC18LF8628T-I/PT
Description
PIC18 With 96KB Flash, 4KB RAM, 1024 DataEE, 12-bit ADC 80 TQFP 12x12x1mm T/R
Manufacturer
Microchip Technology
Series
PIC® 18Fr

Specifications of PIC18LF8628T-I/PT

Core Processor
PIC
Core Size
8-Bit
Speed
40MHz
Connectivity
EBI/EMI, I²C, SPI, UART/USART
Peripherals
Brown-out Detect/Reset, HLVD, POR, PWM, WDT
Number Of I /o
70
Program Memory Size
96KB (48K x 16)
Program Memory Type
FLASH
Eeprom Size
1K x 8
Ram Size
3.8K x 8
Voltage - Supply (vcc/vdd)
2 V ~ 5.5 V
Data Converters
A/D 16x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
80-TFQFP
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Other names
PIC18LF8628T-I/PTTR

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Part Number
Manufacturer
Quantity
Price
Part Number:
PIC18LF8628T-I/PT
Manufacturer:
MICROCHIP
Quantity:
12 000
Part Number:
PIC18LF8628T-I/PT
Manufacturer:
Microchip Technology
Quantity:
10 000
2.6
When the LVP Configuration bit is ‘1’ (see Section 5.3
“Single-Supply
Low-Voltage ICSP mode is enabled. As shown in
Figure 2-9, Low-Voltage ICSP Program/Verify mode is
entered by holding PGC and PGD low, placing a logic
high on PGM and then raising MCLR/V
In this mode, the RB5/PGM pin is dedicated to the
programming function and ceases to be a general
purpose I/O pin. Figure 2-10 shows the exit sequence.
The sequence that enters the device into the Program/
Verify mode places all unused I/Os in the high-impedance
state.
FIGURE 2-9:
FIGURE 2-10:
© 2009 Microchip Technology Inc.
PGM
PGD
PGC
MCLR/V
V
MCLR/V
V
PGD
PGC
PGM
DD
DD
Entering and Exiting Low-Voltage
ICSP Program/Verify Mode
PP
PP
/RG5
/RG5
V
IH
ICSP
V
PGD = Input
PGD = Input
IH
P15
ENTERING LOW-VOLTAGE
PROGRAM/VERIFY MODE
EXITING LOW-VOLTAGE
PROGRAM/VERIFY MODE
V
P16
IH
Programming”),
P12
V
P18
IH
PP
/RG5 to V
the
IH
.
2.7
The PGC pin is used as a clock input pin and the PGD
pin is used for entering command bits and data input/
output during serial operation. Commands and data are
transmitted on the rising edge of PGC, latched on the
falling edge of PGC and are Least Significant bit (LSb)
first.
2.7.1
All instructions are 20 bits, consisting of a leading 4-bit
command followed by a 16-bit operand, which depends
on the type of command being executed. To input a
command, PGC is cycled four times. The commands
needed for programming and verification are shown in
Table 2-4. Commands and data are entered, LSb first.
Depending on the 4-bit command, the 16-bit operand
represents 16 bits of input data or 8 bits of input data
and 8 bits of output data.
Throughout this specification, commands and data are
presented as illustrated in Table 2-5. The 4-bit command
and data are shown, Most Significant bit (MSb) first. The
command operand, or “Data Payload”, is shown
<LSB><MSB>. Figure 2-11 demonstrates how to serially
present a 20-bit command/operand to the device.
2.7.2
The core instruction passes a 16-bit instruction to the
CPU core for execution. This is needed to set up
registers as appropriate for use with other commands.
TABLE 2-4:
TABLE 2-5:
PIC18F872X FAMILY
Core Instruction (shift in16-bit instruction)
Shift Out TABLAT Register
Table Read
Table Read, Post-Increment
Table Read, Post-Decrement
Table Read, Pre-Increment
Table Write
Table Write, Post-Increment by 2
Table Write, Start Programming,
Post-Increment by 2
Table Write, Start Programming
Command
1101
4-Bit
Serial Program/Verify Operation
4-BIT COMMANDS
CORE INSTRUCTION
Description
Payload
3C 40
Data
COMMANDS FOR
PROGRAMMING
SAMPLE COMMAND
SEQUENCE
Table Write,
post-increment by 2
Core Instruction
DS39643C-page 9
Command
0000
0010
1000
1001
1010
1011
1100
1101
1110
1111
4-Bit

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