PIC18LF6723T-I/PT Microchip Technology, PIC18LF6723T-I/PT Datasheet - Page 13

• Manufacturer Part Number: PIC18LF6723T-I/PT
• Description: PIC18 With 128KB Flash, 4KB RAM, 1024 DataEE, 12-bit ADC 64 TQFP 10x10x1mm T/R
• Manufacturer: Microchip Technology
• Series: PIC® 18Fr

Specifications of PIC18LF6723T-I/PT

• Core Processor: PIC
• Core Size: 8-Bit
• Speed: 40MHz
• Connectivity: I²C, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, HLVD, POR, PWM, WDT
• Number Of I /o: 54
• Program Memory Size: 128KB (64K x 16)
• Program Memory Type: FLASH
• Eeprom Size: 1K x 8
• Ram Size: 3.8K x 8
• Voltage - Supply (vcc/vdd): 2 V ~ 5.5 V
• Data Converters: A/D 12x12b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 64-TFQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: PIC18LF6723T-I/PTTR

FIGURE 3-2:
3.1.2
When using low-voltage ICSP, the part must be
supplied by the voltage specified in parameter, D111, if
a Bulk Erase is to be executed. All other Bulk Erase
details as described above apply.
If it is determined that a program memory erase must
be performed at a supply voltage below the Bulk Erase
limit, refer to the erase methodology described in
Section 3.1.3 “ICSP Row Erase” and Section 3.2.2
“Modifying Code Memory”.
If it is determined that a data EEPROM erase must be
performed at a supply voltage below the Bulk Erase
limit, follow the methodology described in Section 3.3
“Data EEPROM Programming” and write ‘1’s to the
array.
© 2009 Microchip Technology Inc.
PGC
PGD
4-Bit Command
1 2
0 0 1 1
LOW-VOLTAGE ICSP BULK ERASE
3
4
P5
BULK ERASE TIMING
1
Data Payload
1 1
2
16-Bit
15 16
0
0
P5A
4-Bit Command
1
0
2
0 0 0
3
PGD = Input
4
P5
1
Data Payload
0
2
0
16-Bit
3.1.3
Regardless of whether high or low-voltage ICSP is
used, it is possible to erase one row (64 bytes of data)
provided the block is not code or write-protected. Rows
are located at static boundaries, beginning at program
memory address, 000000h, extending to the internal
program memory limit (see Section 2.3 “Memory
Maps”).
The Row Erase duration is externally timed and is
controlled by PGC. After the WR bit in EECON1 is set,
a NOP is issued, where the 4th PGC is held high for the
duration of the programming time, P9.
After PGC is brought low, the programming sequence
is terminated. PGC must be held low for the time
specified by parameter, P10, to allow high-voltage
discharge of the memory array.
The code sequence to Row Erase a PIC18F872X family
device is shown in Table 3-3. The flowchart shown in
Figure 3-3 depicts the logic necessary to completely
erase a PIC18F872X family device. The timing diagram
that details the Start Programming command and
parameters, P9 and P10, is shown in Figure 3-4.
PIC18F872X FAMILY
15 16
Note:
0
0
P5A
4-Bit Command
1
0 0 0 0
ICSP ROW ERASE
The TBLPTR register can point to any byte
within the row intended for erase.
2
3
4
Erase Time
P11
DS39643C-page 13
P10
Data Payload
16-Bit
1
n
2
n