PIC18F45K20-E/MV Microchip Technology, PIC18F45K20-E/MV Datasheet - Page 395
![32KB, Flash, 1536bytes-RAM, 36I/O, 8-bit Family,nanowatt XLP 40 UQFN 5x5x0.5mm T](/photos/16/15/161538/qfn-40_sml.jpg)
PIC18F45K20-E/MV
Manufacturer Part Number
PIC18F45K20-E/MV
Description
32KB, Flash, 1536bytes-RAM, 36I/O, 8-bit Family,nanowatt XLP 40 UQFN 5x5x0.5mm T
Manufacturer
Microchip Technology
Series
PIC® XLP™ 18Fr
Datasheet
1.PIC18F25K20T-ISS.pdf
(456 pages)
Specifications of PIC18F45K20-E/MV
Processor Series
PIC18
Core
PIC18F
Data Bus Width
8 bit
Program Memory Type
Flash
Program Memory Size
8 KB
Data Ram Size
512 B
Interface Type
I2C, SPI, SCI, USB, MSSP, RJ11
Maximum Clock Frequency
64 MHz
Number Of Programmable I/os
35
Number Of Timers
4
Operating Supply Voltage
1.8 V to 3.6 V
Maximum Operating Temperature
+ 125 C
Mounting Style
SMD/SMT
Package / Case
UQFN-40
Development Tools By Supplier
MPLAB Integrated Development Environment
Minimum Operating Temperature
- 40 C
Operating Temperature Range
- 40 C to + 125 C
Supply Current (max)
30 uA
Core Processor
PIC
Core Size
8-Bit
Speed
48MHz
Connectivity
I²C, SPI, UART/USART
Peripherals
Brown-out Detect/Reset, HLVD, POR, PWM, WDT
Number Of I /o
35
Eeprom Size
256 x 8
Ram Size
1.5K x 8
Voltage - Supply (vcc/vdd)
1.8 V ~ 3.6 V
Data Converters
A/D 14x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 125°C
Lead Free Status / Rohs Status
Details
- Current page: 395 of 456
- Download datasheet (4Mb)
FIGURE 26-15:
TABLE 26-17: EXAMPLE SPI SLAVE MODE REQUIREMENTS (CKE = 1)
2010 Microchip Technology Inc.
Param
70
71
71A
72
72A
73A
74
75
76
77
78
79
80
82
83
Note 1:
No.
Note:
(CKP = 0)
(CKP = 1)
SDI
SDI
SS
SCK
SCK
SDO
2:
TssL2scH,
TssL2scL
TscH
TscL
Tb2b
TscH2diL,
TscL2diL
TdoR
TdoF
TssH2doZ SS to SDO Output High-Impedance
TscR
TscF
TscH2doV,
TscL2doV
TssL2doV SDO Data Output Valid after SS Edge
TscH2ssH
,
TscL2ssH
Symbol
Requires the use of Parameter #73A.
Only if Parameter #71A and #72A are used.
Refer to Figure 26-4 for load conditions.
SS to SCK or SCK Input
SCK Input High Time
(Slave mode)
SCK Input Low Time
(Slave mode)
Last Clock Edge of Byte 1 to the First Clock Edge of Byte 2 1.5 T
Hold Time of SDI Data Input to SCK Edge
SDO Data Output Rise Time
SDO Data Output Fall Time
SCK Output Rise Time
(Master mode)
SCK Output Fall Time (Master mode)
SDO Data Output Valid after SCK Edge
SS after SCK Edge
82
EXAMPLE SPI SLAVE MODE TIMING (CKE = 1)
70
MSb In
MSb
74
71
75, 76
Characteristic
72
bit 6 - - - - - -1
bit 6 - - - -1
Continuous
Single Byte
Continuous
Single Byte
80
PIC18F2XK20/4XK20
LSb In
LSb
1.25 T
1.25 T
1.5 T
Min
T
100
CY
CY
40
40
10
—
—
—
—
—
—
CY
CY
CY
83
+ 40
+ 40
+ 30
+ 30
77
Max Units Conditions
25
25
50
25
25
50
50
—
—
—
—
—
—
—
—
DS41303G-page 395
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
(Note 1)
(Note 1)
(Note 2)
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