PIC18F45K20-E/MV Microchip Technology, PIC18F45K20-E/MV Datasheet - Page 306
![32KB, Flash, 1536bytes-RAM, 36I/O, 8-bit Family,nanowatt XLP 40 UQFN 5x5x0.5mm T](/photos/16/15/161538/qfn-40_sml.jpg)
PIC18F45K20-E/MV
Manufacturer Part Number
PIC18F45K20-E/MV
Description
32KB, Flash, 1536bytes-RAM, 36I/O, 8-bit Family,nanowatt XLP 40 UQFN 5x5x0.5mm T
Manufacturer
Microchip Technology
Series
PIC® XLP™ 18Fr
Datasheet
1.PIC18F25K20T-ISS.pdf
(456 pages)
Specifications of PIC18F45K20-E/MV
Processor Series
PIC18
Core
PIC18F
Data Bus Width
8 bit
Program Memory Type
Flash
Program Memory Size
8 KB
Data Ram Size
512 B
Interface Type
I2C, SPI, SCI, USB, MSSP, RJ11
Maximum Clock Frequency
64 MHz
Number Of Programmable I/os
35
Number Of Timers
4
Operating Supply Voltage
1.8 V to 3.6 V
Maximum Operating Temperature
+ 125 C
Mounting Style
SMD/SMT
Package / Case
UQFN-40
Development Tools By Supplier
MPLAB Integrated Development Environment
Minimum Operating Temperature
- 40 C
Operating Temperature Range
- 40 C to + 125 C
Supply Current (max)
30 uA
Core Processor
PIC
Core Size
8-Bit
Speed
48MHz
Connectivity
I²C, SPI, UART/USART
Peripherals
Brown-out Detect/Reset, HLVD, POR, PWM, WDT
Number Of I /o
35
Eeprom Size
256 x 8
Ram Size
1.5K x 8
Voltage - Supply (vcc/vdd)
1.8 V ~ 3.6 V
Data Converters
A/D 14x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 125°C
Lead Free Status / Rohs Status
Details
- Current page: 306 of 456
- Download datasheet (4Mb)
PIC18F2XK20/4XK20
REGISTER 23-10: CONFIG7L: CONFIGURATION REGISTER 7 LOW
REGISTER 23-11: CONFIG7H: CONFIGURATION REGISTER 7 HIGH
DS41303G-page 306
bit 7
Legend:
R = Readable bit
-n = Value when device is unprogrammed
bit 7-4
bit 3
bit 2
bit 1
bit 0
Note 1:
bit 7
Legend:
R = Readable bit
-n = Value when device is unprogrammed
bit 7
bit 6
bit 5-0
U-0
U-0
—
—
Implemented, but not used in PIC18FX3K20 and PIC18FX4K20 devices.
Unimplemented: Read as ‘0’
EBTR3: Table Read Protection bit
1 = Block 3 not protected from table reads executed in other blocks
0 = Block 3 protected from table reads executed in other blocks
EBTR2: Table Read Protection bit
1 = Block 2 not protected from table reads executed in other blocks
0 = Block 2 protected from table reads executed in other blocks
EBTR1: Table Read Protection bit
1 = Block 1 not protected from table reads executed in other blocks
0 = Block 1 protected from table reads executed in other blocks
EBTR0: Table Read Protection bit
1 = Block 0 not protected from table reads executed in other blocks
0 = Block 0 protected from table reads executed in other blocks
Unimplemented: Read as ‘0’
EBTRB: Boot Block Table Read Protection bit
1 = Boot Block not protected from table reads executed in other blocks
0 = Boot Block protected from table reads executed in other blocks
Unimplemented: Read as ‘0’
EBTRB
R/C-1
U-0
—
U-0
U-0
—
—
U-0
(1)
U-0
(1)
—
—
U = Unimplemented bit, read as ‘0’
C = Clearable only bit
U = Unimplemented bit, read as ‘0’
C = Clearable only bit
EBTR3
R/C-1
U-0
—
(1)
EBTR2
R/C-1
U-0
—
(1)
2010 Microchip Technology Inc.
EBTR1
R/C-1
U-0
—
EBTR0
R/C-1
U-0
—
bit 0
bit 0
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