PIC18F25K80T-I/MM Microchip Technology, PIC18F25K80T-I/MM Datasheet - Page 179
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PIC18F25K80T-I/MM
Manufacturer Part Number
PIC18F25K80T-I/MM
Description
ECAN, 32KB Flash, 4KB RAM, 16 MIPS, 12-bit ADC, CTMU 28 QFN-S 6x6mm T/R
Manufacturer
Microchip Technology
Series
PIC® XLP™ 18Fr
Datasheet
1.PIC18F25K80-ISO.pdf
(628 pages)
Specifications of PIC18F25K80T-I/MM
Core Processor
PIC
Core Size
8-Bit
Speed
64MHz
Connectivity
ECAN, I²C, LIN, SPI, UART/USART
Peripherals
Brown-out Detect/Reset, LVD, POR, PWM, WDT
Number Of I /o
24
Program Memory Size
32KB (16K x 16)
Program Memory Type
FLASH
Eeprom Size
1K x 8
Ram Size
3.6K x 8
Voltage - Supply (vcc/vdd)
1.8 V ~ 5.5 V
Data Converters
A/D 8x12b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
*
Processor Series
PIC18F25K80
Core
PIC
Data Bus Width
8 bit
Data Ram Size
3648 B
Interface Type
I2C, SPI
Maximum Clock Frequency
64 MHz
Number Of Programmable I/os
24
Number Of Timers
5
Operating Supply Voltage
1.8 V to 5.5 V
Maximum Operating Temperature
+ 125 C
Mounting Style
SMD/SMT
Minimum Operating Temperature
- 40 C
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
PIC18F25K80T-I/MM
Manufacturer:
MICROCHIP
Quantity:
3 000
- Current page: 179 of 628
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11.1.3
The output pins for several peripherals are also
equipped with a configurable, open-drain output option.
This allows the peripherals to communicate with
external digital logic, operating at a higher voltage
level, without the use of level translators.
The open-drain option is implemented on port pins
specifically associated with the data and clock outputs
of the USARTs, the MSSP module (in SPI mode) and
the CCP modules. This option is selectively enabled by
setting the open-drain control bits in the ODCON
register.
When the open-drain option is required, the output pin
must also be tied through an external pull-up resistor
provided by the user to a higher voltage level, up to 5V
(Figure
it is pulled up to the higher voltage level.
REGISTER 11-3:
2011 Microchip Technology Inc.
bit 7
Legend:
R = Readable bit
-n = Value at POR
bit 7
bit 6
bit 5
bit 4
bit 3
bit 2
bit 1
bit 0
SSPOD
R/W-0
11-2). When a digital logic high signal is output,
OPEN-DRAIN OUTPUTS
SSPOD: SPI Open-Drain Output Enable bit
1 = Open-drain capability enabled
0 = Open-drain capability disabled
CCP5OD: CCP5 Open-Drain Output Enable bit
1 = Open-drain capability enabled
0 = Open-drain capability disabled
CCP4OD: CCP4 Open-Drain Output Enable bit
1 = Open-drain capability enabled
0 = Open-drain capability disabled
CCP3OD: CCP3 Open-Drain Output Enable bit
1 = Open-drain capability enabled
0 = Open-drain capability disabled
CCP2OD: CCP2 Open-Drain Output Enable bit
1 = Open-drain capability enabled
0 = Open-drain capability disabled
CCP1OD: CCP1 Open-Drain Output Enable bit
1 = Open-drain capability enabled
0 = Open-drain capability disabled
U2OD: UART2 Open-Drain Output Enable bit
1 = Open-drain capability enabled
0 = Open-drain capability disabled
U1OD: UART1 Open-Drain Output Enable bit
1 = Open-drain capability enabled
0 = Open-drain capability disabled
CCP5OD
R/W-0
ODCON: PERIPHERAL OPEN-DRAIN CONTROL REGISTER
W = Writable bit
‘1’ = Bit is set
CCP4OD
R/W-0
CCP3OD
R/W-0
Preliminary
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared
PIC18F66K80 FAMILY
CCP2OD
R/W-0
FIGURE 11-2:
3.3V
V
CCP1OD
DD
PIC18F66K80
R/W-0
(at logic ‘1’)
USING THE OPEN-DRAIN
OUTPUT (USART SHOWN
AS EXAMPLE)
TX
x = Bit is unknown
X
R/W-0
U2OD
3.3V
DS39977C-page 179
+5V
R/W-0
U1OD
5V
bit 0
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