PIC16F721T-I/SO Microchip Technology, PIC16F721T-I/SO Datasheet - Page 98

• Manufacturer Part Number: PIC16F721T-I/SO
• Description: 7 KB FLASH, 256 B SRAM, 18 I/O 20 SOIC .300in T/R
• Manufacturer: Microchip Technology
• Series: PIC® XLP™ 16Fr

Specifications of PIC16F721T-I/SO

• Core Processor: PIC
• Core Size: 8-Bit
• Speed: 16MHz
• Connectivity: I²C, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, POR, PWM, WDT
• Number Of I /o: 17
• Program Memory Size: 7KB (4K x 14)
• Program Memory Type: FLASH
• Ram Size: 256 x 8
• Voltage - Supply (vcc/vdd): 1.8 V ~ 5.5 V
• Data Converters: A/D 12x8b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: *
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

PIC16F/LF720/721
13.5.2.1
The T1G pin is one source for Timer1 gate control. It
can be used to supply an external source to the Timer1
gate circuitry.
13.5.2.2
When Timer0 increments from FFh to 00h, a low-to-
high pulse will automatically be generated and
internally supplied to the Timer1 gate circuitry.
13.5.2.3
The TMR2 register will increment until it matches the
value in the PR2 register. On the very next increment
cycle, TMR2 will be reset to 00h. When this Reset
occurs, a low-to-high pulse will automatically be
generated and internally supplied to the Timer1 gate
circuitry.
TABLE 13-5:
DS41430A-page 98
WDTE
1
1
0
0
T1G Pin Gate Operation
Timer0 Overflow Gate Operation
Timer2 Match Gate Operation
WDT/TIMER1 GATE INTERACTION
TMR1GE = 1
T1GSS = 11
and
N
N
Y
Y
WDT Oscillator
Enable
Y
Y
Y
N
WDT Reset
13.5.2.4
The Watchdog Timer oscillator, prescaler and counter
will be automatically turned on when TMR1GE = 1 and
T1GSS selects the WDT as a gate source for Timer1
(T1GSS = 11). TMR1ON does not factor into the oscil-
lator, prescaler and counter enable. See
The PSA and PS bits of the OPTION register still
control what time-out interval is selected. Changing the
prescaler during operation may result in a spurious
capture.
Enabling the Watchdog Timer oscillator does not
automatically enable a Watchdog Reset or Wake-up
from Sleep upon counter overflow.
As the gate signal coming from the WDT counter will
generate different pulse widths depending on if the
WDT is enabled, when the CLRWDT instruction is
executed, and so on, Toggle mode must be used. A
specific sequence is required to put the device into the
correct state to capture the next WDT counter interval.
Note:
Y
Y
N
N
When using the WDT as a gate source for
Timer1, operations that clear the Watchdog
Timer (CLRWDT, SLEEP instructions) will
affect the time interval being measured.
This includes waking from Sleep. All other
interrupts that might wake the device from
Sleep should be disabled to prevent them
from disturbing the measurement period.
Watchdog Overflow Gate Operation
Wake-up
Y
Y
N
N
 2010 Microchip Technology Inc.
WDT Available for
T1G Source
Table
N
Y
Y
N
13-5.