PIC16F721-E/SS Microchip Technology, PIC16F721-E/SS Datasheet - Page 123

• Manufacturer Part Number: PIC16F721-E/SS
• Description: 7 KB FLASH, 256 B SRAM, 18 I/O 20 SSOP .209in TUBE
• Manufacturer: Microchip Technology
• Series: PIC® XLP™ 16Fr

Specifications of PIC16F721-E/SS

• Core Processor: PIC
• Core Size: 8-Bit
• Speed: 16MHz
• Connectivity: I²C, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, POR, PWM, WDT
• Number Of I /o: 17
• Program Memory Size: 7KB (4K x 14)
• Program Memory Type: FLASH
• Ram Size: 256 x 8
• Voltage - Supply (vcc/vdd): 1.8 V ~ 5.5 V
• Data Converters: A/D 12x8b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 125°C
• Package / Case: *
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

TABLE 16-1:
16.1.2
The Asynchronous mode is typically used in RS-232
systems. The receiver block diagram is shown in
Figure
drives the data recovery block. The data recovery block
is actually a high-speed shifter operating at 16 times
the baud rate, whereas the serial Receive Shift
Register (RSR) operates at the bit rate. When all 8 or 9
bits of the character have been shifted in, they are
immediately transferred to a two character First-In
First-Out (FIFO) memory. The FIFO buffering allows
reception of two complete characters and the start of a
third character before software must start servicing the
AUSART receiver. The FIFO and RSR registers are not
directly accessible by software. Access to the received
data is via the RCREG register.
 2010 Microchip Technology Inc.
INTCON
PIE1
PIR1
RCSTA
SPBRG
TRISC
TXREG
TXSTA
Legend:
Name
16-2. The data is received on the RX/DT pin and
x = unknown, - = unimplemented read as ‘0’. Shaded cells are not used for asynchronous transmission.
TMR1GIE
TMR1GIF
AUSART ASYNCHRONOUS
RECEIVER
TRISC7
SPEN
BRG7
CSRC
Bit 7
GIE
REGISTERS ASSOCIATED WITH ASYNCHRONOUS TRANSMISSION
TRISC6
BRG6
PEIE
ADIE
ADIF
Bit 6
RX9
TX9
TMR0IE
TRISC5
SREN
BRG5
TXEN
RCIE
RCIF
Bit 5
AUSART Transmit Data Register
TRISC4
CREN
SYNC
BRG4
Bit 4
INTE
TXIE
TXIF
ADDEN
TRISC3
RABIE
SSPIE
SSPIF
BRG3
Bit 3
—
TMR0IF
CCP1IE
CCP1IF
TRISC2
16.1.2.1
The AUSART receiver is enabled for asynchronous
operation by configuring the following three control bits:
• CREN = 1
• SYNC = 0
• SPEN = 1
All other AUSART control bits are assumed to be in
their default state.
Setting the CREN bit of the RCSTA register enables the
receiver circuitry of the AUSART. Clearing the SYNC bit
of the TXSTA register configures the AUSART for
asynchronous operation. Setting the SPEN bit of the
RCSTA register enables the AUSART and automatically
configures the RX/DT I/O pin as an input.
BRGH
FERR
BRG2
Bit 2
Note:
PIC16F/LF720/721
TMR2IE
TMR2IF
TRISC1
OERR
TRMT
BRG1
Bit 1
INTF
When the SPEN bit is set, the TX/CK I/O
pin is automatically configured as an
output, regardless of the state of the
corresponding TRIS bit and whether or
not the AUSART transmitter is enabled.
The PORT latch is disconnected from the
output driver so it is not possible to use the
TX/CK pin as a general purpose output.
Enabling the Receiver
TMR1IE
TMR1IF
TRISC0
RABIF
RX9D
BRG0
TX9D
Bit 0
0000 000x
0000 0000
0000 0000
0000 000x
0000 0000
1111 1111
0000 0000
0000 -010
POR, BOR
Value on
DS41430A-page 123
0000 000x
0000 0000
0000 0000
0000 000x
0000 0000
1111 1111
0000 0000
0000 -010
Value on
all other
Resets