AM79C03JC AMD (ADVANCED MICRO DEVICES), AM79C03JC Datasheet - Page 22

• Manufacturer Part Number: AM79C03JC
• Manufacturer: AMD (ADVANCED MICRO DEVICES)

Specifications of AM79C03JC

• Lead Free Status / RoHS Status: Supplier Unconfirmed

Operating the DSLAC Device
The following describes the operation of either channel
of the DSLAC device. The description is valid for either
Channel 1 or 2. VIN in this data sheet refers to either
VIN
and CS refers to either CS1 or CS2.
Power-Up Sequence from V
The recommended power-up sequence is to apply:
The software initialization should then include:
Software initialization of the DSLAC device should al-
ways follow any power-up or hardware reset.
Upon initial application of power, a minimum of 1 ms is
needed before CS1 or CS2 may go Low and an MPI
command initiated. If the power supply (VCCD
VCCD
reset and requires complete reprogramming with the
above sequence. Bit 7 of the SLIC Direction Register
reads back as a logical 1 to indicate that a power inter-
ruption has been detected. This bit is cleared when a
software reset command is sent to the DSLAC device.
The RST pin may be tied to +5 V if it is not needed in
the system (Am79C02 only).
Active Mode
Each channel of the DSLAC device can operate in either
the Active (operational) or Inactive (standby) mode. In
the Active mode, the DSLAC device is able to transmit
and receive PCM and analog information. This is the
normal operating mode when a telephone call is in
progress. The Activate command, Microprocessor In-
terface (MPI) Command 5, puts the device into this
state. Bringing the DSLAC device into the Active mode
is possible only through the MPI.
Inactive Mode
The DSLAC device is forced into the Inactive (standby)
mode after a powerup, hardware or software reset, or
is programmed into this mode by the Deactivate com-
mand (Command 1). Power is switched off from all non-
essential circuitry, though the MPI remains active to
receive new commands. The analog output is tied to
ground through an approximate 3 k
cuits, which contain programmed information, retain
their data in the Inactive mode.
22
1. Power supply grounds
2. V
3. Signal connections
4. Hardware Reset (02 only)
1. Select MCLK (Command 6)
2. Software Reset (Command 2)
3. Program filter coefficients and other parameters
4. Activate (Command 5)
1
or VIN
CC
2
) falls below approximately 2.0 V, the device is
/V
EE
2
, VOUT refers to either VOUT
CC
= 0 V
resistor. All cir-
Am79C02/03/031(A) Data Sheet
1
or VOUT
1
or
2
,
Reset State
An active Low, hardware Reset pin (RST) is available
on the Am79C02, which resets the device to the fol-
lowing default state. (For the Am79C02, Am79C03,
and Am79C031, when power is first applied, an internal
power-up reset puts the device into the following de-
fault state.)
10. DXB/DRB ports are selected for Channel 2.
11. MCLK is selected to be 4.096 MHz.
12. Transmit on the negative edge of PCLK. (XE = 0)
13. PCM Delay is inserted.
Reset states 1 to 7 are identical to those of the software
reset (Command 2). The software reset command af-
fects only those channels that have their CS asserted.
Signal Processing
Overview of Digital Filters
Several of the blocks in the signal processing section
are user programmable. These allow the user to opti-
mize the performance of the DSLAC device for the sys-
tem. Figure 8 shows the DSLAC device signal
processing and indicates the programmable blocks.
The advantages of digital filters are:
Two-Wire Impedance Matching
Two feedback paths on the DSLAC device modify the
effective two-wire input impedance of the SLIC by pro-
viding programmable feedback from V
Analog Impedance Scaling Network (AISN) is a pro-
grammable analog gain of –0.9375 to +0.935 from V
to V
connecting V
1. A-law is selected
2. B, X, R, and Z filters disabled; AISN gain is zero.
3. Digital (GX and GR) gain blocks are disabled,
4. SLIC input/output direction is set to the Input mode.
5. Normal conditions are selected (see Command 4).
6. The B-filter Adaptive mode is turned off.
7. Both channels placed in Inactive (standby) mode.
8. Transmit time, receive time, and clock slots are set
9. DXA/DRA ports are selected for Channel 1.
High reliability
No drift with time or temperature
Unit-to-unit repeatability
Superior transmission performance
OUT
resulting in unity gain, and analog (AX and AR)
gains are set to unity.
to zero.
Note: Must be reassigned to DXA/DRA for
Am79C031.
. The Z filter is a programmable digital filter, also
IN
to V
OUT
.
IN
to V
OUT
. The
IN