AM79C03JC AMD (ADVANCED MICRO DEVICES), AM79C03JC Datasheet - Page 11

• Manufacturer Part Number: AM79C03JC
• Manufacturer: AMD (ADVANCED MICRO DEVICES)

Specifications of AM79C03JC

• Lead Free Status / RoHS Status: Supplier Unconfirmed

Transmission Characteristics
The gain of the receive path is defined to be 0 dB when a 0 dBm0, 1014 Hz PCM sine wave input results in a nominal
1.55 Vrms for µ-law or 1.56 Vrms for A-law analog output. The gain of the transmit path is 0 dB when a 1.55 Vrms
for µ-law or 1.56 Vrms for A-law, 1014 Hz sine wave analog input results in a level of 0 dBm0 at the digital output.
When relative levels (dBm0) are used in any of the following transmission specifications, the specification holds for any
setting of the AX + GX gain from 0 to 12 dB and the AR + GR loss from 0 to 12 dB. Performance specification for
settings of the AX + GX gain from 12 to 18 dB and the AR + GR loss from 12 to 18 dB is determined as the device
is characterized.
Notes:
1. AMD guarantees less than 0.1% of units fall into the last 0.05 dB of these specification numbers.
2. See Figure 1.
3. With f swept between 0 to 300 Hz and 3400 to 12 kHz, any generated output signals other than f are less than –28 dBm0.
4. AMD guarantees < 0.2% of units are above –46 dB. This relaxed specification applies to only the third harmonic.
5. Intermodulation distortion specification for two signals of same level in the range of –4 dBm0 to –21 dBm0 does not produce
6. No single frequency component in the range above 3800 Hz may exceed a level of –55 dBm0.
7. The Group Delay specification is defined as the sum of the minimum values of the group delays for the transmit and the
Gain accuracy
D to A or A to D
Gain accuracy
D to A or A to D
Gain accuracy
analog to analog
or digital to digital
Attenuation distortion
Single frequency distortion, A to D
Single frequency distortion, D to A –6 dB < (GR + AR) < 0 dB
Intermodulation distortion
Idle channel noise
Crosstalk
same channel
Crosstalk
between channels
Group delay PCLK
This specification is valid for either transmission path.
2
to 3400 Hz at –9 dBm0.
receive paths when the transmit and receive time slots are identical and the B, X, R, and Z filters are disabled. For PCLK
frequencies between 1.03 MHz and 1.53 MHz, the group delay may vary from one cycle to the next. See Figure 2.
•
(f1 – f2) component above specified level. 50 Hz IMD specified with 50 Hz signal at –23 dBm0 and signal between 300 Hz
Description
PCLK
Analog out
Digital out
1.53 MHz
1.03 MHz
RX to RX
TX to RX
RX to TX
TX to RX
RX to TX
TX to TX
0 dBm0, 1014 Hz
0 dB < |path gain| < 6 dB
0 dBm0, 1014 Hz
6 dB < |path gain| < 12 dB
–12 dB < (GR + AR) < –6 dB
–12 dB < (GR + AR) < –6 dB
–12 dB < (GR + AR) < –6 dB
–12 dB < (GR + AR) < –6 dB
digital looped back
digital input = 0
analog V
0 dBm0
0 dBm0
B, X, R, and Z filters disabled
IN
= 0
Test Conditions
SLAC Products
300 Hz to 3400 Hz
300 Hz to 3400 Hz
300 Hz to 3400 Hz
–40°C to 85°C
25°C to 85°C
70°C to 85°C
25°C to 85°C
70°C to 85°C
unweighted
weighted
–40°C
–40°C
–40°C
–40°C
A-law
A-law
µ-law
µ-law
25°C
25°C
0°C
0°C
0°C
0°C
–0.125
–0.20
–0.25
–0.35
–0.20
–0.25
–0.30
–0.35
–0.20
–0.25
–0.35
Min
Typ
+0.125
+0.20
+0.25
+0.35
+0.20
+0.25
+0.30
+0.35
+0.20
+0.25
+0.35
Max
–46
–46
–46
–45
–43
–40
–42
–56
–68
–55
–78
–68
–75
–75
–76
–78
–76
–78
630
695
12
19
dBrnc0
dBrnc0
dBm0p
dBm0p
dBm0p
dBm0p
Unit
dBr
dB
µs
Note
3, 4
3, 4
3, 4
—
—
1
1
2
3
3
3
5
6
7
11