HC55185ECM Intersil, HC55185ECM Datasheet - Page 9

• Manufacturer Part Number: HC55185ECM
• Manufacturer: Intersil

Specifications of HC55185ECM

• Number Of Channels: 1
• On-hook Transmission: Yes
• Polarity Reversal: Yes
• On-chip Ring Relay Driver: Yes
• Longitudinal Balanced: 64
• Operating Supply Voltage (typ): 5/-18/-24/-28V
• Operating Temp Range: 0C to 85C
• Package Type: PLCC
• Loop Current Limit: 45mA
• Operating Temperature Classification: Commercial
• Pin Count: 28
• Mounting: Surface Mount
• Operating Current: 10.3mA
• Operating Supply Voltage (max): 5.25/-52V
• Operating Supply Voltage (min): 4.75/-16V
• Lead Free Status / RoHS Status: Not Compliant

Design Equations
Loop Supervision Thresholds
SWITCH HOOK DETECT
The switch hook detect threshold is set by a single external
resistor, R
The term I
loop current threshold programming range is from 5mA to
15mA.
GROUND KEY DETECT
The ground key detector senses a DC current imbalance
between the Tip and Ring terminals when the ring terminal is
connected to ground. The ground key detect threshold is not
externally programmable and is internally fixed to 12mA
regardless of the switch hook threshold.
RING TRIP DETECT
The ring trip detect threshold is set by a single external
resistor, R
current and the peak off hook current while still ringing.
In addition, the ring trip current must be set below the
transient current limit, including tolerances. The capacitor
C
Loop Current Limit
The loop current limit of the device is programmed by the
external resistor R
using Equation 5:
The term I
current limit programming range is from 15mA to 45mA.
Impedance Matching
The impedance of the device is programmed with the
external component R
the feedback amplifier that provides impedance matching. If
complex impedance matching is required, then a complex
network can be substituted for R
RESISTIVE IMPEDANCE SYNTHESIS
The source impedance of the device, Z
in Equation 6.
The required impedance is defined by the terminating
impedance and protection resistors as shown in Equation 7.
R
R
R
R
Z
RT
IL
S
O
SH
RT
=
, in parallel with R
=
=
=
=
133.3 Z
Z
1760
------------ -
I
LIM
1800 I
L
600 I
–
SH
RT
SH
LIM
2R
(
⁄
. Equation 3 is used to calculate the value of R
⁄
. I
SH
O
P
is the desired DC loop current threshold. The
RT
is the desired loop current limit. The loop
RT
)
should be set between the peak ringing
IL
. The value of R
RT
S
. R
, will set the ring trip response time.
S
is the gain setting resistor for
9
S
.
IL
can be calculated
O
, can be calculated
(EQ. 5)
(EQ. 4)
(EQ. 3)
(EQ. 6)
(EQ. 7)
SH
HC55185
.
4-WIRE TO 2-WIRE GAIN
The 4-wire to 2-wire gain is defined as the receive gain. It is
a function of the terminating impedance, synthesized
impedance and protection resistors. Equation 8 calculates
the receive gain, G
When the device source impedance and protection resistors
equals the terminating impedance, the receive gain equals
unity.
2-WIRE TO 4-WIRE GAIN
The 2-wire to 4-wire gain (G
the VTX output. The transmit gain is calculated in Equation 9.
When the protection resistors are set to zero, the transmit
gain is -6dB.
TRANSHYBRID GAIN
The transhybrid gain is defined as the 4-wire to 4-wire gain
(G
When the protection resistors are set to zero, the transhybrid
gain is -6dB.
COMPLEX IMPEDANCE SYNTHESIS
Substituting the impedance programming resistor, R
complex programming network provides complex
impedance synthesis.
The reference designators in the programming network
match the evaluation board. The component R
different design equation than the R
impedance synthesis. The design equations for each
component are provided below.
G
R
R
C
G
G
44
Series
Parallel
Parallel
24
42
44
).
=
=
=
FIGURE 2. COMPLEX PROGRAMMING NETWORK
–
–
–
⎛
⎜
⎝
⎛
⎜
⎝
=
2
-------------------------------------- -
Z
----------------------------------------- -
Z
=
=
⎛
⎜
⎝
O
R
O
133.3
----------------------------------------- -
Z
1
133.3
C
O
+
+ 2R
2
2R
+ 2R
Z
NETWORK
⁄
Z
O
133.3
2-WIRE
·
×
O
Z
P
P
×
C
R
(
L
+
R
42
P
R
2
2
+ Z
Z
1
2
+ Z
.
L
–
⎞
⎟
⎠
L
2 R
⎞
⎟
⎠
L
(
⎞
⎟
⎠
24
P
)
) is the gain from tip and ring to
)
R
S
Series
used for resistive
PROGRAMMING
NETWORK
R
C
Parallel
Parallel
S
December 18, 2006
has a
S
(EQ. 12)
(EQ. 13)
FN4831.14
(EQ. 10)
(EQ. 11)
, with a
(EQ. 9)
(EQ. 8)