CYP15G0402DXB-BGI Cypress Semiconductor Corp, CYP15G0402DXB-BGI Datasheet - Page 7

• Manufacturer Part Number: CYP15G0402DXB-BGI
• Manufacturer: Cypress Semiconductor Corp

Specifications of CYP15G0402DXB-BGI

• Lead Free Status / RoHS Status: Not Compliant

Document #: 38-02057 Rev. *G
Pin Descriptions
Transmit Path Data Signals
TXPERA
TXPERB
TXPERC
TXPERD
TXDA[9:0]
TXDB[9:0]
TXDC[9:0]
TXDD[9:0]
TXOPA
TXOPB
TXOPC
TXOPD
Transmit Path Clock and Control
TXCLKO±
TXCKSEL
TXCLKA
TXCLKB
TXCLKC
TXCLKD
Notes:
4.
5.
When REFCLK is configured for half-rate operation (TXRATE = HIGH), these inputs are sampled (or the outputs change) relative to both the rising and falling
edges of REFCLK
Three-level select inputs are used for static configuration. They are ternary (not binary) inputs that make use of non-standard logic levels of LOW, MID, and
HIGH. The LOW level is usually implemented by direct connection to V
not connected or allowed to float, a three-level select input will self-bias to the MID level.
Name
LVTTL1 Output,
changes relative to
REFCLK↑
LVTTL Input,
synchronous,
sampled by the
respective TXCLKx↑
or REFCLK↑
LVTTL Input,
synchronous,
sampled by the
respective TXCLKx↑
or REFCLK↑
LVTTL Output
Three-level Select
Static Control Input
LVTTL Clock Input
asynchronous,
internal pull-up
I/O Characteristics Signal Description
CYP(V)15G0402DXB Quad HOTLink II™ SERDES
[4]
[4]
[4]
[5]
Transmit Path Parity Error. Active HIGH. Asserted (HIGH) if parity checking is enabled
and a parity error is detected at the shifter. This output is HIGH for one transmit character
clock period to indicate detection of a parity error in the character presented to the
shifter.
If a parity error is detected, the character in error is replaced with the 10-bit character,
1001111000, to force a corresponding bad-character detection at the remote end of the
link. This replacement takes place only when parity checking is enabled (PARCTL ≠
LOW).
When BIST is enabled for the specific transmit channel, BIST progress is presented on
these outputs. Once every 511 character times, the associated TXPERx signal will pulse
HIGH for one transmit-character clock period to indicate a complete pass through the
BIST sequence.
These outputs also provide indication of a transmit Phase-Align Buffer underflow or
overflow. When the transmit Phase-Align Buffers are enabled (TXCKSEL ≠ LOW, or
TXCKSEL = LOW and TXRATE = HIGH), if an underflow or overflow condition is
detected, TXPERx for the channel in error is asserted and remains asserted until either
an atomic Word Sync Sequence is transmitted or TXRST is sampled LOW to re-center
the transmit Phase-Align Buffers.
Transmit Data Inputs. These inputs are captured on the rising edge of the transmit
interface clock as selected by TXCKSEL and passed to the transmit shifter.
TXDx[9:0] specify the specific transmission character to be sent.
Transmit Path Odd Parity. When parity checking is enabled (PARCTL ≠ LOW), the
ODD parity captured at these inputs is XORed with the bits on the associated TXDx bus
to verify the integrity of the captured character.
Transmit Clock Output. This true and complement clock is synthesized by the transmit
PLL and is synchronous to the internal transmit character clock. It has the same
frequency as REFCLK (when TXRATE = LOW), or twice the frequency of REFCLK
(when TXRATE = HIGH). This output clock has no direct phase relationship to REFCLK.
Transmit Clock Select.
Selects the clock source used to write data into the transmit Input Register of the
transmit channel(s)
When LOW, all four input registers are clocked by REFCLK↑.
When TXCKSEL is MID, TXCLKx↑ is used as the input register clock for the associated
TXDx[9:0] and TXOPx.
When HIGH, TXCLKA↑ is used to clock data into the Input Register for all channels.
When TXCKSEL = MID or HIGH (TXCLKx or TXCLKA selected to clock input register),
TXRATE = HIGH (Half-rate REFCLK) is an invalid mode of operation.
Transmit Path Input Clocks. These inputs are only used when TXCKSEL ≠ LOW.
These clocks must be frequency-coherent to REFCLK, but may be offset in phase.
The internal operating phase of each input clock (relative to REFLCK or TXCLKO±) is
adjusted when TXRST = LOW and locked when TXRST = HIGH.
SS
(ground). The HIGH level is usually implemented by direct connection to V
CYP15G0402DXB
CYV15G0402DXB
Page 7 of 29
CC
. When
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