CYP15G0402DXB-BGI Cypress Semiconductor Corp, CYP15G0402DXB-BGI Datasheet - Page 12

• Manufacturer Part Number: CYP15G0402DXB-BGI
• Manufacturer: Cypress Semiconductor Corp

Specifications of CYP15G0402DXB-BGI

• Lead Free Status / RoHS Status: Not Compliant

Document #: 38-02057 Rev. *G
Table 1. Input Register Bit Mapping
Phase-Align Buffer
Data from the Input Registers is normally routed to the
associated Phase-Align Buffer. When the transmit paths are
operated synchronous to REFCLK↑ (TXCKSEL = LOW and
TXRATE = LOW), the Phase-Align Buffers are bypassed and
data is passed directly to the Parity Check and Serializer
blocks to reduce latency.
When an Input-Register clock with an uncontrolled phase
relationship to REFCLK is selected (TXCKSEL ≠ LOW) or if
data is captured on both edges of REFCLK (TXRATE = HIGH),
the Phase-Align Buffers are enabled. These buffers are used
to absorb clock phase differences between the presently
selected input clock and the internal character clock.
Initialization of these Phase-Align Buffers takes place when
the TXRST input is sampled LOW by two consecutive rising
edges of REFCLK
present input clock phase relative to REFCLK is set. TXRST
is an asynchronous input, but is sampled internally to
synchronize it to the internal transmit path state machines.
Once set, the input clocks are allowed to skew in time up to
half a character period in either direction relative to REFCLK;
i.e., ±180°. This time shift allows the delay paths of the
character clocks (relative to REFCLK) to change due to
operating voltage and temperature, while not affecting reliable
data transfer.
If the phase offset, between the initialized location of the input
clock and REFCLK↑, exceeds the skew handling capabilities
of the Phase-Align Buffer, an error is reported on the
associated TXPERx output. This output indicates a continuous
error until the Phase-Align Buffer is reset. While the error
remains active, the transmitter for the associated channel will
output a continuous 10-bit character, 1001111000b, to indicate
to the remote receiver that an error condition is present in the
link.
Parity Support
In addition to the ten data bits that are captured at each
channel, a TXOPx input is also available on each channel.
This allows the CYP(V)15G0402DXB to support ODD parity
Notes:
6.
7.
TXDx[0]
TXDx[9]
Signal Name
LSB is shifted out first.
The TXOPx inputs are also captured in the associated Input Register, but their interpretation is under the separate control of PARCTL.
TXOPx
TXDx[1]
TXDx[2]
TXDx[3]
TXDx[4]
TXDx[5]
TXDx[6]
TXDx[7]
TXDx[8]
(LSB)
(MSB)
[7]
[6]
↑
. When TXRST is returned HIGH, the
Bus Weight
2
2
2
2
2
2
2
2
2
2
0
1
2
3
4
5
6
7
8
9
10B Name
a
b
c
d
e
g
h
i
f
j
checking for each channel. When PARCTL = LOW, parity
checking is disabled. When PARCTL = MID or HIGH, parity is
checked on the TXDx[9:0] and TXOPx bits.
If parity checking is enabled (PARCTL ≠ LOW) and a parity
error is detected, the 10-bit character in error is replaced with
the 1001111000b pattern (an invalid character).
Transmit BIST
The transmitter interfaces contain internal pattern generators
that can be used to validate both device and link operation.
These generators are enabled by the associated BOE[x]
signals listed in Table 2 (when the BISTLE latch enable input
is HIGH). When enabled, a register in the associated transmit
channel becomes a signature pattern generator by logically
converting to a Linear Feedback Shift Register (LFSR). This
LFSR generates a 511-character sequence that includes all
Data and Special Character codes, including the explicit
violation
pseudo-random sequence that can be matched to an identical
LFSR in the attached Receiver(s).
When the BISTLE signal is HIGH, any BOE[x] input that is
LOW enables the BIST generator in the associated transmit
channel (or the BIST checker in the associated receive
channel). When BISTLE returns LOW, the values of all BOE[x]
signals are captured in the BIST Enable Latch. These values
remain in the BIST Enable Latch until BISTLE is returned
HIGH to open the latch. A device reset (TRSTZ sampled LOW)
presets the BIST Enable Latch to disable BIST on all channels.
All data and data-control information present at the associated
TXDx[9:0] inputs are ignored when BIST is active on that
channel.
Table 2. Output Enable, BIST, and Receive Channel
Enable Signal Map
Serial Output Drivers
The serial interface Output Drivers use differential CML
(Current Mode Logic) to provide a source-matched driver for
the transmission lines. These drivers accept data from the
Transmit Shifters. These outputs have signal swings equiv-
alent to that of standard PECL drivers and are capable of
driving AC-coupled optical modules or transmission lines.
BOE[7]
BOE[6]
BOE[5]
BOE[4]
BOE[3]
BOE[2]
BOE[1]
BOE[0]
Input
BOE
symbols.
Controlled
(OELE)
OUTD±
OUTC±
OUTB±
Output
OUTA±
X
X
X
X
This
provides
CYP15G0402DXB
CYV15G0402DXB
Transmit D
Transmit C
Transmit B
Transmit A
Receive D
Receive C
Receive B
Receive A
(BISTLE)
Channel
Enable
BIST
a
predictable
Page 12 of 29
Receive PLL
Receive D
Receive C
Receive B
Receive A
Channel
Enable
(RXLE)
X
X
X
X
yet
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