SI3056-D-FSR Silicon Laboratories Inc, SI3056-D-FSR Datasheet - Page 58

• Manufacturer Part Number: SI3056-D-FSR
• Description: Modem Chip Chipset 56Kbps 16-Pin SOIC T/R
• Manufacturer: Silicon Laboratories Inc

Specifications of SI3056-D-FSR

• Package: 16SOIC
• Main Category: Chipset
• Maximum Data Rate: 56 Kbps
• Typical Operating Supply Voltage: 3.3 V
• Power Supply Type: Analog
• Typical Supply Current: 15 mA
• Minimum Operating Supply Voltage: 3 V
• Maximum Operating Supply Voltage: 3.6 V
• Lead Free Status / RoHS Status: Compliant

Si3018/19/10
Register 14. Serial Interface Control
Reset settings = 0000_0000 (serial mode 0,1)
Reset settings = 0011_1101 (serial mode 2)
58
Bit
7:5
4:3
Name
Type
2
1
0
Bit
NSLV[2:0] Number of Slaves devices.
SSEL[1:0] Slave device select.
Name
RPOL
DCE
FSD
D7
NSLV[2:0]
000 = 0 slaves. Redefines the FC/RGDT and RGDT/FSD pins.
001 = 1 slave device
010 = 2 slave devices
011 = 3 slave devices
100 = 4 slave devices (For four or more slave devices, the FSD bit MUST be set.)
101 = 5 slave devices
110 = 6 slave devices
111 = 7 slave devices
00 = 16-bit SDO receive data
01 = Reserved
10 = 15-bit SDO receive data, LSB = 1
11 = 15-bit SDO receive data, LSB = 0
Delayed Frame Sync Control.
0 = Sets the number of SCLK periods between frame syncs to 32.
1 = Sets the number of SCLK periods between frame syncs to 16. This bit MUST be set when
Si3056 devices are slaves. For the master Si3056, only serial mode 1 is allowed when this bit
is set.
Ring Detect Polarity.
0 = The FC/RGDT pin (operating as ring detect) is active low.
1 = The FC/RGDT pin (operating as ring detect) is active high.
Daisy-Chain Enable.
0 = Daisy-chaining disabled.
1 = Enables the Si3056 to operate with slave devices on the same serial bus. The FC/RGDT
signal (pin 7) becomes the ring detect output and the RDGT/FSD signal (pin 15) becomes the
delayed frame sync signal. ALL other bits in this register are ignored if DCE = 0.
R/W
D6
D5
D4
SSEL[1:0]
R/W
D3
Rev. 1.05
FSD
R/W
D2
Function
RPOL
R/W
D1
DCE
R/W
D0