AD9875BSTZ Analog Devices Inc, AD9875BSTZ Datasheet - Page 2

• Manufacturer Part Number: AD9875BSTZ
• Manufacturer: Analog Devices Inc

Specifications of AD9875BSTZ

• Main Category: Single Chip
• Sub-category: Converter
• Power Supply Type: Analog/Digital
• Operating Supply Voltage (typ): 3.3V
• Package Type: LQFP
• Operating Supply Voltage (min): 3V
• Operating Supply Voltage (max): 3.6V
• Supply Current: 262mA
• Operating Temp Range: -40C to 85C
• Operating Temperature Classification: Industrial
• Pin Count: 48
• Mounting: Surface Mount
• Lead Free Status / RoHS Status: Compliant

AD9875–SPECIFICATIONS
Parameter
OSC IN CHARACTERISTICS
CLOCK OUTPUT CHARACTERISTICS
Tx CHARACTERISTICS
Rx PATH CHARACTERISTICS
Frequency Range
Duty Cycle
Input Capacitance
Input Impedance
CLKA Jitter (f
CLKA Duty Cycle
CLKB Jitter (f
CLKB Duty Cycle
Tx Path Latency, 4× Interpolation
Interpolation Filter Bandwidth (–0.1 dB)
TxDAC
Resolution
Conversion Rate
Pipeline Delay, ADC Clock Cycles
DC Accuracy
Dynamic Performance
Signal-to-Noise Ratio (SNR)
Dynamic Performance
4× Interpolation, LPF
2× Interpolation, LPF
Resolution
Conversion Rate
Full-Scale Output Current
Voltage Compliance Range
Gain Error
Output Offset
Differential Nonlinearity
Integral Nonlinearity
Output Capacitance
Phase Noise @ 1 kHz Offset, 10 MHz Signal
Signal-to-Noise and Distortion (SINAD)
Wideband SFDR (to Nyquist, 64 MHz Max)
Narrowband SFDR (3 MHz Window)
IMD (f1 = 6.9 MHz, f2 = 7.1 MHz)
Differential Nonlinearity
Integral Nonlinearity
(A
@ f
Signal-to-Noise and Distortion Ratio (SINAD)
Effective Number of Bits (ENOB)
Total Harmonic Distortion (THD)
Spurious Free Dynamic Range (SFDR)
(A
@ F
Signal-to-Noise and Distortion Ratio (SINAD)
Effective Number of Bits (ENOB)
Signal-to-Noise Ratio (SNR)
Total Harmonic Distortion (THD)
Spurious Free Dynamic Range (SFDR)
10 MHz Analog Out AD9875 (20 MHz BW)
5 MHz Analog Out
10 MHz Analog Out
10 MHz Analog Out
IN
IN
OSCIN
PLLB/2
= –0.5 dBFS, f = 10 MHz)
= –0.5 dBFS, f = 5 MHz)
= 32 MHz
= 50 MHz
CLKA
CLKB
Derived from PLL)
Derived from PLL)
(V
100
S
Temp
Full
25°C
25°C
25°C
25°C
25°C
25°C
25°C
Full
Full
Full
Full
Full
Full
Full
Full
Full
25°C
25°C
25°C
25°C
Full
25°C
25°C
25°C
25°C
25°C
Full
Full
Full
25°C
25°C
25°C
25°C
25°C
25°C
25°C
25°C
25°C
25°C
25°C
25°C
= 3.3 V
DAC single-ended load, unless otherwise noted.)
–2–
10%, f
Test
Level
II
II
III
III
III
III
III
III
II
II
II
II
II
II
II
II
II
III
III
III
III
I
III
III
III
III
III
II
II
II
II
II
III
III
III
III
III
III
III
III
III
III
OSCIN
= 32 MHz, f
Min
10
40
10
2
–0.5
–5
0
59
7.5
–1.0
–2.0
DAC
= 128 MHz, Gain = –6 dB, R
Typ
50
3
100
14
50 ± 5
33
50 ± 5
82
13
26
10
10
± 2
7
0.5
5
–90
61
78
72
80
–76
10
± 0.25
± 0.5
59.6
9.5
60
–65
68
54
8.6
55
–61
68
5.5
Max
64
60
128
20
+1.5
+5
19
1
55
+1.0
+2.0
SET
= 4.02 k ,
Unit
MHz
%
pF
MΩ
ps rms
%
ps rms
%
f
MHz
MHz
Bits
MHz
mA
V
% FS
µA
LSB
LSB
pF
dBc/Hz
dB
dBc
dBc
dBc
dBFS
Bits
MHz
Cycles
LSB
LSB
dB
Bits
dB
dB
dB
dB
Bits
dB
dB
dB
DAC
Cycles
REV. A