AD9875BSTZ Analog Devices Inc, AD9875BSTZ Datasheet - Page 16

• Manufacturer Part Number: AD9875BSTZ
• Manufacturer: Analog Devices Inc

Specifications of AD9875BSTZ

• Main Category: Single Chip
• Sub-category: Converter
• Power Supply Type: Analog/Digital
• Operating Supply Voltage (typ): 3.3V
• Package Type: LQFP
• Operating Supply Voltage (min): 3V
• Operating Supply Voltage (max): 3.6V
• Supply Current: 262mA
• Operating Temp Range: -40C to 85C
• Operating Temperature Classification: Industrial
• Pin Count: 48
• Mounting: Surface Mount
• Lead Free Status / RoHS Status: Compliant

AD9875
typically drive a resistive load which will convert the output
currents to a voltage. The Tx+ and Tx– output currents are
inherently ground seeking and should each be connected to
matching resistors, R
The full-scale output current of the DAC is set by the value of
the resistor placed from the FSADJ pin to AGND. The relation-
ship between the resistor, R
is governed by the following equation:
The full-scale current can be set from 2 mA to 20 mA. Gener-
ally, there is a trade-off between DAC performance and power
consumption. The best DAC performance will be realized at an
I
overall current consumption of the device.
The single-ended voltage output appearing at the Tx+ and
Tx– nodes are:
Note that the full-scale voltage of V
the maximum output compliance range of 1.5 V to prevent signal
compression. To maintain optimum distortion and linearity
performance, the maximum voltages at V
exceed 0.5 V.
The single ended full-scale voltage at either output node will be:
The differential voltage, V
For optimum performance, a differential output interface is
recommended since any common-mode noise or distortion can
be suppressed.
It should be noted that the differential output impedance of the
DAC is 2 × R
resistors will load down the output voltage accordingly.
RECEIVE PATH DESCRIPTION
The receive path consists of a two-stage PGA, a continuous time,
4-pole LPF, an ADC, a digital HPF and a digital data multiplexer.
Also working in conjunction with the receive path is an offset
correction circuit and a digital phase lock loop. Each of these
blocks will be discussed in detail in the following sections.
Programmable Gain Amplifier
The PGA has a programmable gain range from –6 dB to +36 dB
if the narrower (approximately 12 MHz) LPF bandwidth is
selected, or if the LPF is bypassed. If the wider (approximately
26 MHz) LPF bandwidth is selected, the gain range is –6 dB to
+30 dB. The PGA is comprised of two sections, a Continuous
Time PGA (CPGA) and a Switched Capacitor PGA (SPGA).
The CPGA has possible gain settings of –6, 0, 6, 12, 18, and 24.
The SPGA has possible gain settings of 0, 2, 4, 6, 8, 10, and 12 dB.
Table I shows how the gain is distributed for each programmed
gain setting.
FS
of 20 mA. However, the value of I
L
and any load connected across the two output
V
DIFF
L
V
, that are tied directly to AGND.
V
DIFF
V
I
V
TX
=
FS
TX
DIFF
FS
(
–
+
—
SET
I
= 39 4 .
TX
FS
=
=
=
, appearing across V
and
, and the full-scale output current
I
I
I
+
=
TX
TX
FS
–
Tx+
I
+
–
FS
×
I
R
TX
×
×
and V
R
SET
×
R
FS
R
–
L
L
)
R
L
adds directly to the
Tx+
×
L
Tx–
R
and V
L
should not exceed
Tx+
Tx–
and V
should not
Tx–
is:
–16–
The CPGA input appears at the device Rx+ and Rx– input pins.
The input impedance of this stage is nominally 270 Ω differen-
tial and is not gain dependent. It is best to ac-couple the input
signal to this stage and let the inputs self bias. This will lower the
offset voltage of the input signal, which is important at higher
gains, as any offset will lower the output compliance range of the
CPGA output. When the inputs are driven by direct coupling, the
dc level should be AVDD/2. However, this could lead to larger dc
offsets and consequently reduce the dynamic range of the Rx path.
Low-Pass Filter
The Low-Pass Filter (LPF) is a programmable, multistage,
fourth order low-pass filter comprised of two real poles and a
complex pole pair. The first real pole is implemented within the
CPGA. The second filter stage implements a complex pair of
poles. The last real pole is implemented in a buffer stage that
drives the SPGA.
There are two passband settings for the LPF. Within each pass-
band the filters are tunable over about a 30% frequency range.
The formula for the cutoff frequency is:
Where Target is the decimal value programmed as the tuning
target in Register 5.
This filter may also be bypassed by setting Bit 0 of Register 4.
In this case, the bandwidth of the Rx path will decrease with
increasing gain and be approximately 50 MHz at the highest gain
settings.
ADC
The AD9875’s analog-to-digital converter implements a pipelined
multistage architecture to achieve high sample rates while con-
suming low power. The ADC distributes the conversion over
several smaller A/D subblocks, refining the conversion with
progressively higher accuracy as it passes the results from stage to
stage. As a consequence of the distributed conversion, ADCs require
a small fraction of the 2
flash-type A/D. A sample-and-hold function within each of the
stages permits the first stage to operate on a new input sample
while the remaining stages operate on preceding samples. Each
stage of the pipeline, excluding the last, consists of a low resolution
flash A/D connected to a switched capacitor DAC and interstage
residue amplifier (MDAC). The residue amplifier amplifies the
difference between the reconstructed DAC output and the flash
input for the next stage in the pipeline. One bit of redundancy is
used in each one of the stages to facilitate digital correction of
flash errors. The last stage simply consists of a flash A/D.
AINN
AINP
f
f
Figure 2. ADC Theory of Operation
CUTOFF LOW
CUTOFF HIGH
A/D
SHA
D/A
N
GAIN
=
=
comparators used in a traditional n-bit
f
f
ADC
ADC
CORRECTION LOGIC
×
×
158 64
64 64
A/D
(
(
SHA
D/A
+
+
T
T
arg
arg
AD9875
GAIN
et
et
)
)
A/D
REV. A