MC33742DW Freescale, MC33742DW Datasheet - Page 47

• Manufacturer Part Number: MC33742DW
• Manufacturer: Freescale

Specifications of MC33742DW

• Data Rate: 1000Kbps
• Number Of Transceivers: 1
• Standard Supported: CAN 2.0
• Operating Supply Voltage (max): 27V
• Operating Supply Voltage (typ): 5/9/12/15/18/24V
• Operating Supply Voltage (min): 4.5V
• Package Type: SOIC W
• Supply Current: 45mA
• Operating Temperature (max): 125C
• Operating Temperature (min): -40C
• Operating Temperature Classification: Automotive
• Mounting: Surface Mount
• Pin Count: 28
• Lead Free Status / RoHS Status: Not Compliant

Table 14. List of Registers
SPI INTERFACE AND REGISTER DESCRIPTION
DATA FORMAT DESCRIPTION
8 bits in a SPI register. The first three bits are used to identify
the internal SBC register address. Bit 4 is a read/write bit.
The last four bits are data sent from the MCU to the SBC or
read back from the 33742 to the MCU.
operation. However, during a read operation the final four bits
of MISO have meaning; namely, they contain the content of
the accessed register.
Analog Integrated Circuit Device Data
Freescale Semiconductor
Note Read operation: R/W bit = logic [0]
:
MISO
Register
Figure 27
The state of the MISO has no significance during the write
WUR
MCR
INTR
RCR
CAN
LPC
IOR
TIM
Write operation: R/W = logic [1]
Bit 7
A2
Figure 27. Data Format Description.
illustrates an 8-bit byte corresponding to the
Address
Bit 6
A1
Address
$000
$001
$010
$011
$100
$101
$110
$111
Bit 5
A0
Mode Control Register (MCR)
Reset Control Register (RCR)
CAN Register (CAN) on page
Timing Register (TIM1 / 2) on
Low Power Control Register
Input / Output Register (IOR)
Interrupt Register (INTR) on
Bit 4
R/W
(LPC) on page 54
Formal Name
Bit 3
D3
on page 48
on page 49
on page 50
on page 51
and Link
page 52
page 56
49
Bit 2
D2
Data
LOGIC COMMANDS AND REGISTERS
Bit 1 Bit 0
D1
D0
• TIM1: Watchdog timing control, Watch-
• TIM2: Cyclic Sense and Forced Wake-
Selection for Normal, Standby, Sleep,
Stop, and Debug modes
Configuration for reset voltage level, CAN Sleep and Stop modes
CAN slew rate, Sleep and Wake-up
enable/disable modes, drive enable after
failure
HS (high side switch) control in Normal
and Standby mode
Control of wake-up input polarity
Control HS periodic activation in Sleep
and Stop modes, Forced Wake-up mode
activation, CAN-INT mode selection
Enable or Disable of Interrupts
dog Window (WDW) or Watchdog Tim-
eout (WTO) mode
up timing selection
MOSI
Table 13. Possible Reset Conditions
REGISTER DESCRIPTIONS
register list and register bit meaning. Register reset values
are also described, along with the reset condition. A reset
condition is the condition causing the bit to be set at the reset
value.
Write
33742 Reset
33742 Mode
Transition
33742 Mode
The following tables in this section describe the SPI
Condition
Comment and Use
STO2NR
NR2STB
STB2R
STO2R
RESET
Name
NR2R
NR2N
POR
N2R
BATFAIL, general failure, VDD pre-
warning, and Watchdog flag
CAN wake-up and CAN failure status bits
HS over-temperature bit, VSUP, and V2
LOW status
Wake-up input and real time Lx input
state
CANL and TXD failure reporting
CANH and RXD failure reporting
Interrupt source
LOGIC COMMANDS AND REGISTERS
FUNCTIONAL DEVICE OPERATION
Power-ON Reset
Normal Request to Standby mode
Normal to Reset mode
Standby to Reset mode
Stop to Reset mode
Stop to Normal Request
33742S in Reset mode
Normal Request to Reset mode
Normal Request to Normal mode
Read
Definition
33742
47