PXB4221EV34NP Lantiq, PXB4221EV34NP Datasheet - Page 74

• Manufacturer Part Number: PXB4221EV34NP
• Manufacturer: Lantiq

Specifications of PXB4221EV34NP

• Data Rate: 2.048Mbps
• Number Of Channels: 1
• Operating Supply Voltage (typ): 3.3V
• Operating Temp Range: -40C to 85C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Lead Free Status / RoHS Status: Not Compliant

interface and which have to be returned because of loopback “lpcr”, have priority over
register “tsinN”.
During this test, the clock recovery or, in case of loopback, the receive FIFO receives the
RTS values written in field rtsi. It is advisable to power down the circuit(s) which do not
work properly with these RTS values via bit “pwd” of “condN”. If “srt” in “condN” is reset,
the output of the RTS Receive FIFO is not used by PLL-SRTS.
4.5.8
The fractional divider generates a 2.43 MHz clock from the 51.84 MHz clock provided via
the CLK52 pin. This is done by selecting 3 out of 64 clock pulses of 51.84 MHz. The
resulting 2.43 MHz clock contains jitter components of 810 kHz and above, with a
maximum peak to peak jitter of 19 ns.
4.5.9
For an overview on the required clocks for the ICRC please refer to
4.5.10
Different Power down modes are available for the ICRC:
• for each port via bit “pwd” in “condN”
• for the Clock Recovery Interface via bit “pdcri” in “icrcconf”.
• for the complete ICRC by means of the “a_icrc_dwn” bit in the “acfg”. This feature
4.5.11
This block is implemented for each port. It consists of 3 PLLs: PLL-SRTS, PLL-ACM and
PLL-FILTER.
The bits “srt” and “acm” in the register “condN” define, which PLL is connected to PLL-
FILTER and used for clock recovery. Each PLL may be used exclusively or in
combination.
4.5.11.1 PLL-SRTS:
PLL-SRTS is used for clock recovery using the SRTS method. It has a cut-off frequency
of 20 to 50 Hz.
The phase detector of PLL-SRTS has a linear range which optimized for jitter tolerance
requirements. It is defined by a “window” of accepted RTS values. Each time PLL-SRTS
detects values, which fall out of the window, or processes invalid values, it is forced in
hold over for 1 SRTS period, bit “hov” of register “statN” is set and the
Data Sheet
reduces the power consumption by approximately 50 mW. Once the ICRC is switched
off, it can only be enabled by hardware reset of the whole device.
Fractional Divider
Clocks
Power Management
PLL Block
74
PXB 4219E, PXB 4220E, PXB 4221E
Operational Description
Chapter
IWE8, V3.4
2003-01-20
8.1.